From: Robert Richter <rrichter@amd.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window
Date: Sat, 17 Feb 2024 22:27:40 +0100 [thread overview]
Message-ID: <ZdEkzBbm7aqcghAl@rric.localdomain> (raw)
In-Reply-To: <65d034a22e258_29b129484@dwillia2-mobl3.amr.corp.intel.com.notmuch>
On 16.02.24 20:22:58, Dan Williams wrote:
> Robert Richter wrote:
> > The Linux CXL subsystem is built on the assumption that HPA == SPA.
> > That is, the host physical address (HPA) the HDM decoder registers are
> > programmed with are system physical addresses (SPA).
> >
> > During HDM decoder setup, the DVSEC CXL range registers (cxl-3.1,
> > 8.1.3.8) are checked if the memory is enabled and the CXL range is in
> > a HPA window that is described in a CFMWS structure of the CXL host
> > bridge (cxl-3.1, 9.18.1.3).
> >
> > Now, if the HPA is not an SPA, the CXL range does not match a CFMWS
> > window and the CXL memory range will be disabled then. The HDM decoder
> > stops working which causes system memory being disabled and further a
> > system hang during HDM decoder initialization, typically when a CXL
> > enabled kernel boots.
> >
> > Prevent a system hang and do not disable the HDM decoder if the
> > decoder's CXL range is not found in a CFMWS window.
> >
> > Note the change only fixes a hardware hang, but does not implement
> > HPA/SPA translation. Support for this can be added in a follow on
> > patch series.
> >
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > ---
> > drivers/cxl/core/pci.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > index a0e7ed5ae25f..18616ca873e5 100644
> > --- a/drivers/cxl/core/pci.c
> > +++ b/drivers/cxl/core/pci.c
> > @@ -478,8 +478,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> > }
> >
> > if (!allowed) {
> > - cxl_set_mem_enable(cxlds, 0);
> > - info->mem_enabled = 0;
> > + dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n");
> > + return -ENXIO;
>
> While testing I found this needs the following fixup:
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index e24ffae8135f..e9e6c81ce034 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -477,7 +477,7 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
> allowed++;
> }
>
> - if (!allowed) {
> + if (!allowed && info->mem_enabled) {
> dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n");
> return -ENXIO;
> }
The change looks correct to me, thanks for fixing.
-Robert
>
>
> ...i.e. Linux should only give up if it does not understand an active
> decode region.
>
> Now this SPA/HPA mismatch will still cause problems later in region
> creation flow, but that's a separate issue.
next prev parent reply other threads:[~2024-02-17 21:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-16 16:01 [PATCH v2] cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window Robert Richter
2024-02-16 18:02 ` Dan Williams
2024-02-16 18:09 ` Robert Richter
2024-02-16 22:04 ` Robert Richter
2024-02-17 3:07 ` Dan Williams
2024-02-17 4:22 ` Dan Williams
2024-02-17 21:27 ` Robert Richter [this message]
2024-03-22 3:15 ` [Problem ?] cxl list show nothing after reboot " Zhijian Li (Fujitsu)
2024-03-26 8:26 ` Zhijian Li (Fujitsu)
2024-04-05 16:57 ` Jonathan Cameron
2024-04-07 3:51 ` Zhijian Li (Fujitsu)
2024-04-08 23:14 ` Dan Williams
2024-04-09 6:53 ` Zhijian Li (Fujitsu)
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