* [PATCH 1/2] clk: keystone: add support for post divider register for main pll
@ 2015-05-29 16:04 Murali Karicheri
[not found] ` <1432915453-409-1-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
2015-06-18 22:37 ` Michael Turquette
0 siblings, 2 replies; 12+ messages in thread
From: Murali Karicheri @ 2015-05-29 16:04 UTC (permalink / raw
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
mturquette-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Murali Karicheri
Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.
Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
---
.../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----
drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt
index 225990f..47570d2 100644
--- a/Documentation/devicetree/bindings/clock/keystone-pll.txt
+++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt
@@ -15,8 +15,8 @@ Required properties:
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
- clocks : parent clock phandle
- reg - pll control0 and pll multipler registers
-- reg-names : control and multiplier. The multiplier is applicable only for
- main pll clock
+- reg-names : control, multiplier and post-divider. The multiplier and
+ post-divider registers are applicable only for main pll clock
- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
for postdiv
@@ -25,8 +25,8 @@ Example:
#clock-cells = <0>;
compatible = "ti,keystone,main-pll-clock";
clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>;
- reg-names = "control", "multiplier";
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
fixed-postdiv = <2>;
};
diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
index 0dd8a4b..4a375ea 100644
--- a/drivers/clk/keystone/pll.c
+++ b/drivers/clk/keystone/pll.c
@@ -37,7 +37,8 @@
* Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
* or PA PLL available on keystone2. These PLLs are controlled by
* this register. Main PLL is controlled by a PLL controller.
- * @pllm: PLL register map address
+ * @pllm: PLL register map address for multiplier bits
+ * @pllod: PLL register map address for post divider bits
* @pll_ctl0: PLL controller map address
* @pllm_lower_mask: multiplier lower mask
* @pllm_upper_mask: multiplier upper mask
@@ -53,6 +54,7 @@ struct clk_pll_data {
u32 phy_pllm;
u32 phy_pll_ctl0;
void __iomem *pllm;
+ void __iomem *pllod;
void __iomem *pll_ctl0;
u32 pllm_lower_mask;
u32 pllm_upper_mask;
@@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
/* read post divider from od bits*/
postdiv = ((val & pll_data->clkod_mask) >>
pll_data->clkod_shift) + 1;
- else
+ else if (pll_data->pllod) {
+ postdiv = readl(pll_data->pllod);
+ postdiv = ((postdiv & pll_data->clkod_mask) >>
+ pll_data->clkod_shift) + 1;
+ } else
postdiv = pll_data->postdiv;
rate /= (prediv + 1);
@@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
/* assume the PLL has output divider register bits */
pll_data->clkod_mask = CLKOD_MASK;
pll_data->clkod_shift = CLKOD_SHIFT;
+
+ /*
+ * Check if there is an post-divider register. If not
+ * assume od bits are part of control register.
+ */
+ i = of_property_match_string(node, "reg-names",
+ "post-divider");
+ pll_data->pllod = of_iomap(node, i);
}
i = of_property_match_string(node, "reg-names", "control");
pll_data->pll_ctl0 = of_iomap(node, i);
if (!pll_data->pll_ctl0) {
pr_err("%s: ioremap failed\n", __func__);
+ iounmap(pll_data->pllod);
goto out;
}
@@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
pll_data->pllm = of_iomap(node, i);
if (!pll_data->pllm) {
iounmap(pll_data->pll_ctl0);
+ iounmap(pll_data->pllod);
goto out;
}
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
[not found] ` <1432915453-409-1-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
@ 2015-05-29 16:04 ` Murali Karicheri
2015-07-31 14:20 ` Murali Karicheri
2015-07-31 15:30 ` santosh shilimkar
2015-06-09 15:25 ` [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
2015-06-15 16:26 ` Murali Karicheri
2 siblings, 2 replies; 12+ messages in thread
From: Murali Karicheri @ 2015-05-29 16:04 UTC (permalink / raw
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
mturquette-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Murali Karicheri
All of the keystone devices have a separate register to hold post
divider value for main pll clock. Currently the fixed-postdiv
value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
use a value of 2 for this. Now that we have fixed this in the pll
clock driver change the dt bindings for the same.
Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/k2e-clocks.dtsi | 5 ++---
arch/arm/boot/dts/k2hk-clocks.dtsi | 5 ++---
arch/arm/boot/dts/k2l-clocks.dtsi | 5 ++---
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi
index 4773d6a..d56d68f 100644
--- a/arch/arm/boot/dts/k2e-clocks.dtsi
+++ b/arch/arm/boot/dts/k2e-clocks.dtsi
@@ -13,9 +13,8 @@ clocks {
#clock-cells = <0>;
compatible = "ti,keystone,main-pll-clock";
clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>;
- reg-names = "control", "multiplier";
- fixed-postdiv = <2>;
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
};
papllclk: papllclk@2620358 {
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi
index d5adee3..af9b719 100644
--- a/arch/arm/boot/dts/k2hk-clocks.dtsi
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -22,9 +22,8 @@ clocks {
#clock-cells = <0>;
compatible = "ti,keystone,main-pll-clock";
clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>;
- reg-names = "control", "multiplier";
- fixed-postdiv = <2>;
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
};
papllclk: papllclk@2620358 {
diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi
index eb1e3e2..ef8464b 100644
--- a/arch/arm/boot/dts/k2l-clocks.dtsi
+++ b/arch/arm/boot/dts/k2l-clocks.dtsi
@@ -22,9 +22,8 @@ clocks {
#clock-cells = <0>;
compatible = "ti,keystone,main-pll-clock";
clocks = <&refclksys>;
- reg = <0x02620350 4>, <0x02310110 4>;
- reg-names = "control", "multiplier";
- fixed-postdiv = <2>;
+ reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
+ reg-names = "control", "multiplier", "post-divider";
};
papllclk: papllclk@2620358 {
--
1.9.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll
[not found] ` <1432915453-409-1-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
2015-05-29 16:04 ` [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll Murali Karicheri
@ 2015-06-09 15:25 ` Murali Karicheri
2015-06-15 16:26 ` Murali Karicheri
2 siblings, 0 replies; 12+ messages in thread
From: Murali Karicheri @ 2015-06-09 15:25 UTC (permalink / raw
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
mturquette-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 05/29/2015 12:04 PM, Murali Karicheri wrote:
> Main PLL controller has post divider bits in a separate register in
> pll controller. Use the value from this register instead of fixed
> divider when available.
>
> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> ---
> .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----
> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt
> index 225990f..47570d2 100644
> --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt
> @@ -15,8 +15,8 @@ Required properties:
> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
> - clocks : parent clock phandle
> - reg - pll control0 and pll multipler registers
> -- reg-names : control and multiplier. The multiplier is applicable only for
> - main pll clock
> +- reg-names : control, multiplier and post-divider. The multiplier and
> + post-divider registers are applicable only for main pll clock
> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
> for postdiv
>
> @@ -25,8 +25,8 @@ Example:
> #clock-cells = <0>;
> compatible = "ti,keystone,main-pll-clock";
> clocks = <&refclksys>;
> - reg = <0x02620350 4>, <0x02310110 4>;
> - reg-names = "control", "multiplier";
> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
> + reg-names = "control", "multiplier", "post-divider";
> fixed-postdiv = <2>;
> };
>
> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
> index 0dd8a4b..4a375ea 100644
> --- a/drivers/clk/keystone/pll.c
> +++ b/drivers/clk/keystone/pll.c
> @@ -37,7 +37,8 @@
> * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
> * or PA PLL available on keystone2. These PLLs are controlled by
> * this register. Main PLL is controlled by a PLL controller.
> - * @pllm: PLL register map address
> + * @pllm: PLL register map address for multiplier bits
> + * @pllod: PLL register map address for post divider bits
> * @pll_ctl0: PLL controller map address
> * @pllm_lower_mask: multiplier lower mask
> * @pllm_upper_mask: multiplier upper mask
> @@ -53,6 +54,7 @@ struct clk_pll_data {
> u32 phy_pllm;
> u32 phy_pll_ctl0;
> void __iomem *pllm;
> + void __iomem *pllod;
> void __iomem *pll_ctl0;
> u32 pllm_lower_mask;
> u32 pllm_upper_mask;
> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
> /* read post divider from od bits*/
> postdiv = ((val & pll_data->clkod_mask) >>
> pll_data->clkod_shift) + 1;
> - else
> + else if (pll_data->pllod) {
> + postdiv = readl(pll_data->pllod);
> + postdiv = ((postdiv & pll_data->clkod_mask) >>
> + pll_data->clkod_shift) + 1;
> + } else
> postdiv = pll_data->postdiv;
>
> rate /= (prediv + 1);
> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
> /* assume the PLL has output divider register bits */
> pll_data->clkod_mask = CLKOD_MASK;
> pll_data->clkod_shift = CLKOD_SHIFT;
> +
> + /*
> + * Check if there is an post-divider register. If not
> + * assume od bits are part of control register.
> + */
> + i = of_property_match_string(node, "reg-names",
> + "post-divider");
> + pll_data->pllod = of_iomap(node, i);
> }
>
> i = of_property_match_string(node, "reg-names", "control");
> pll_data->pll_ctl0 = of_iomap(node, i);
> if (!pll_data->pll_ctl0) {
> pr_err("%s: ioremap failed\n", __func__);
> + iounmap(pll_data->pllod);
> goto out;
> }
>
> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
> pll_data->pllm = of_iomap(node, i);
> if (!pll_data->pllm) {
> iounmap(pll_data->pll_ctl0);
> + iounmap(pll_data->pllod);
> goto out;
> }
> }
>
Dear Maintainers?
Any comments please? If not, can this be applied?
--
Murali Karicheri
Linux Kernel, Keystone
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll
[not found] ` <1432915453-409-1-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
2015-05-29 16:04 ` [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll Murali Karicheri
2015-06-09 15:25 ` [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
@ 2015-06-15 16:26 ` Murali Karicheri
2 siblings, 0 replies; 12+ messages in thread
From: Murali Karicheri @ 2015-06-15 16:26 UTC (permalink / raw
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
mturquette-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 05/29/2015 12:04 PM, Murali Karicheri wrote:
> Main PLL controller has post divider bits in a separate register in
> pll controller. Use the value from this register instead of fixed
> divider when available.
>
> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> ---
> .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----
> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt
> index 225990f..47570d2 100644
> --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt
> @@ -15,8 +15,8 @@ Required properties:
> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
> - clocks : parent clock phandle
> - reg - pll control0 and pll multipler registers
> -- reg-names : control and multiplier. The multiplier is applicable only for
> - main pll clock
> +- reg-names : control, multiplier and post-divider. The multiplier and
> + post-divider registers are applicable only for main pll clock
> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
> for postdiv
>
> @@ -25,8 +25,8 @@ Example:
> #clock-cells = <0>;
> compatible = "ti,keystone,main-pll-clock";
> clocks = <&refclksys>;
> - reg = <0x02620350 4>, <0x02310110 4>;
> - reg-names = "control", "multiplier";
> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
> + reg-names = "control", "multiplier", "post-divider";
> fixed-postdiv = <2>;
> };
>
> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
> index 0dd8a4b..4a375ea 100644
> --- a/drivers/clk/keystone/pll.c
> +++ b/drivers/clk/keystone/pll.c
> @@ -37,7 +37,8 @@
> * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
> * or PA PLL available on keystone2. These PLLs are controlled by
> * this register. Main PLL is controlled by a PLL controller.
> - * @pllm: PLL register map address
> + * @pllm: PLL register map address for multiplier bits
> + * @pllod: PLL register map address for post divider bits
> * @pll_ctl0: PLL controller map address
> * @pllm_lower_mask: multiplier lower mask
> * @pllm_upper_mask: multiplier upper mask
> @@ -53,6 +54,7 @@ struct clk_pll_data {
> u32 phy_pllm;
> u32 phy_pll_ctl0;
> void __iomem *pllm;
> + void __iomem *pllod;
> void __iomem *pll_ctl0;
> u32 pllm_lower_mask;
> u32 pllm_upper_mask;
> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
> /* read post divider from od bits*/
> postdiv = ((val & pll_data->clkod_mask) >>
> pll_data->clkod_shift) + 1;
> - else
> + else if (pll_data->pllod) {
> + postdiv = readl(pll_data->pllod);
> + postdiv = ((postdiv & pll_data->clkod_mask) >>
> + pll_data->clkod_shift) + 1;
> + } else
> postdiv = pll_data->postdiv;
>
> rate /= (prediv + 1);
> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
> /* assume the PLL has output divider register bits */
> pll_data->clkod_mask = CLKOD_MASK;
> pll_data->clkod_shift = CLKOD_SHIFT;
> +
> + /*
> + * Check if there is an post-divider register. If not
> + * assume od bits are part of control register.
> + */
> + i = of_property_match_string(node, "reg-names",
> + "post-divider");
> + pll_data->pllod = of_iomap(node, i);
> }
>
> i = of_property_match_string(node, "reg-names", "control");
> pll_data->pll_ctl0 = of_iomap(node, i);
> if (!pll_data->pll_ctl0) {
> pr_err("%s: ioremap failed\n", __func__);
> + iounmap(pll_data->pllod);
> goto out;
> }
>
> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
> pll_data->pllm = of_iomap(node, i);
> if (!pll_data->pllm) {
> iounmap(pll_data->pll_ctl0);
> + iounmap(pll_data->pllod);
> goto out;
> }
> }
>
DT and CLK maintainers,
A gentle reminder to review and provide your comments or acks.
Thanks and regards,
--
Murali Karicheri
Linux Kernel, Keystone
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll
2015-05-29 16:04 [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
[not found] ` <1432915453-409-1-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
@ 2015-06-18 22:37 ` Michael Turquette
2015-06-18 22:55 ` santosh shilimkar
1 sibling, 1 reply; 12+ messages in thread
From: Michael Turquette @ 2015-06-18 22:37 UTC (permalink / raw
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
ssantosh, sboyd, devicetree, linux-kernel, linux-clk, linux,
linux-arm-kernel
Cc: Murali Karicheri
Quoting Murali Karicheri (2015-05-29 09:04:12)
> Main PLL controller has post divider bits in a separate register in
> pll controller. Use the value from this register instead of fixed
> divider when available.
>
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Applied to clk-next.
Regards,
Mike
> ---
> .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----
> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--
> 2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt
> index 225990f..47570d2 100644
> --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt
> @@ -15,8 +15,8 @@ Required properties:
> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
> - clocks : parent clock phandle
> - reg - pll control0 and pll multipler registers
> -- reg-names : control and multiplier. The multiplier is applicable only for
> - main pll clock
> +- reg-names : control, multiplier and post-divider. The multiplier and
> + post-divider registers are applicable only for main pll clock
> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
> for postdiv
>
> @@ -25,8 +25,8 @@ Example:
> #clock-cells = <0>;
> compatible = "ti,keystone,main-pll-clock";
> clocks = <&refclksys>;
> - reg = <0x02620350 4>, <0x02310110 4>;
> - reg-names = "control", "multiplier";
> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
> + reg-names = "control", "multiplier", "post-divider";
> fixed-postdiv = <2>;
> };
>
> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c
> index 0dd8a4b..4a375ea 100644
> --- a/drivers/clk/keystone/pll.c
> +++ b/drivers/clk/keystone/pll.c
> @@ -37,7 +37,8 @@
> * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
> * or PA PLL available on keystone2. These PLLs are controlled by
> * this register. Main PLL is controlled by a PLL controller.
> - * @pllm: PLL register map address
> + * @pllm: PLL register map address for multiplier bits
> + * @pllod: PLL register map address for post divider bits
> * @pll_ctl0: PLL controller map address
> * @pllm_lower_mask: multiplier lower mask
> * @pllm_upper_mask: multiplier upper mask
> @@ -53,6 +54,7 @@ struct clk_pll_data {
> u32 phy_pllm;
> u32 phy_pll_ctl0;
> void __iomem *pllm;
> + void __iomem *pllod;
> void __iomem *pll_ctl0;
> u32 pllm_lower_mask;
> u32 pllm_upper_mask;
> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
> /* read post divider from od bits*/
> postdiv = ((val & pll_data->clkod_mask) >>
> pll_data->clkod_shift) + 1;
> - else
> + else if (pll_data->pllod) {
> + postdiv = readl(pll_data->pllod);
> + postdiv = ((postdiv & pll_data->clkod_mask) >>
> + pll_data->clkod_shift) + 1;
> + } else
> postdiv = pll_data->postdiv;
>
> rate /= (prediv + 1);
> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
> /* assume the PLL has output divider register bits */
> pll_data->clkod_mask = CLKOD_MASK;
> pll_data->clkod_shift = CLKOD_SHIFT;
> +
> + /*
> + * Check if there is an post-divider register. If not
> + * assume od bits are part of control register.
> + */
> + i = of_property_match_string(node, "reg-names",
> + "post-divider");
> + pll_data->pllod = of_iomap(node, i);
> }
>
> i = of_property_match_string(node, "reg-names", "control");
> pll_data->pll_ctl0 = of_iomap(node, i);
> if (!pll_data->pll_ctl0) {
> pr_err("%s: ioremap failed\n", __func__);
> + iounmap(pll_data->pllod);
> goto out;
> }
>
> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
> pll_data->pllm = of_iomap(node, i);
> if (!pll_data->pllm) {
> iounmap(pll_data->pll_ctl0);
> + iounmap(pll_data->pllod);
> goto out;
> }
> }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll
2015-06-18 22:37 ` Michael Turquette
@ 2015-06-18 22:55 ` santosh shilimkar
[not found] ` <55834C64.6020703-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: santosh shilimkar @ 2015-06-18 22:55 UTC (permalink / raw
To: Michael Turquette, Murali Karicheri, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, ssantosh, sboyd, devicetree,
linux-kernel, linux-clk, linux, linux-arm-kernel
On 6/18/2015 3:37 PM, Michael Turquette wrote:
> Quoting Murali Karicheri (2015-05-29 09:04:12)
>> Main PLL controller has post divider bits in a separate register in
>> pll controller. Use the value from this register instead of fixed
>> divider when available.
>>
>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
>
> Applied to clk-next.
>
Thanks Mike !!
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll
[not found] ` <55834C64.6020703-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
@ 2015-06-22 20:15 ` Murali Karicheri
0 siblings, 0 replies; 12+ messages in thread
From: Murali Karicheri @ 2015-06-22 20:15 UTC (permalink / raw
To: santosh shilimkar, Michael Turquette,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, ssantosh-DgEjT+Ai2ygdnm+yROfE0A,
sboyd-sgV2jX0FEOL9JmXXK+q4OQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 06/18/2015 06:55 PM, santosh shilimkar wrote:
> On 6/18/2015 3:37 PM, Michael Turquette wrote:
>> Quoting Murali Karicheri (2015-05-29 09:04:12)
>>> Main PLL controller has post divider bits in a separate register in
>>> pll controller. Use the value from this register instead of fixed
>>> divider when available.
>>>
>>> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
>>
>> Applied to clk-next.
>>
> Thanks Mike !!
>
>
Thanks Mike.
Regards,
--
Murali Karicheri
Linux Kernel, Keystone
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
2015-05-29 16:04 ` [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll Murali Karicheri
@ 2015-07-31 14:20 ` Murali Karicheri
2015-07-31 15:30 ` santosh shilimkar
2015-07-31 15:30 ` santosh shilimkar
1 sibling, 1 reply; 12+ messages in thread
From: Murali Karicheri @ 2015-07-31 14:20 UTC (permalink / raw
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
ssantosh, mturquette, sboyd, devicetree, linux-kernel, linux-clk,
linux, linux-arm-kernel
On 05/29/2015 12:04 PM, Murali Karicheri wrote:
> All of the keystone devices have a separate register to hold post
> divider value for main pll clock. Currently the fixed-postdiv
> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
> use a value of 2 for this. Now that we have fixed this in the pll
> clock driver change the dt bindings for the same.
>
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> ---
> arch/arm/boot/dts/k2e-clocks.dtsi | 5 ++---
> arch/arm/boot/dts/k2hk-clocks.dtsi | 5 ++---
> arch/arm/boot/dts/k2l-clocks.dtsi | 5 ++---
> 3 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi
> index 4773d6a..d56d68f 100644
> --- a/arch/arm/boot/dts/k2e-clocks.dtsi
> +++ b/arch/arm/boot/dts/k2e-clocks.dtsi
> @@ -13,9 +13,8 @@ clocks {
> #clock-cells = <0>;
> compatible = "ti,keystone,main-pll-clock";
> clocks = <&refclksys>;
> - reg = <0x02620350 4>, <0x02310110 4>;
> - reg-names = "control", "multiplier";
> - fixed-postdiv = <2>;
> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
> + reg-names = "control", "multiplier", "post-divider";
> };
>
> papllclk: papllclk@2620358 {
> diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi
> index d5adee3..af9b719 100644
> --- a/arch/arm/boot/dts/k2hk-clocks.dtsi
> +++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
> @@ -22,9 +22,8 @@ clocks {
> #clock-cells = <0>;
> compatible = "ti,keystone,main-pll-clock";
> clocks = <&refclksys>;
> - reg = <0x02620350 4>, <0x02310110 4>;
> - reg-names = "control", "multiplier";
> - fixed-postdiv = <2>;
> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
> + reg-names = "control", "multiplier", "post-divider";
> };
>
> papllclk: papllclk@2620358 {
> diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi
> index eb1e3e2..ef8464b 100644
> --- a/arch/arm/boot/dts/k2l-clocks.dtsi
> +++ b/arch/arm/boot/dts/k2l-clocks.dtsi
> @@ -22,9 +22,8 @@ clocks {
> #clock-cells = <0>;
> compatible = "ti,keystone,main-pll-clock";
> clocks = <&refclksys>;
> - reg = <0x02620350 4>, <0x02310110 4>;
> - reg-names = "control", "multiplier";
> - fixed-postdiv = <2>;
> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
> + reg-names = "control", "multiplier", "post-divider";
> };
>
> papllclk: papllclk@2620358 {
>
Santosh,
The clk driver update is already merged to v4.2-rc. Could you send this
DT update as well for 4.2-rc?
Murali
--
Murali Karicheri
Linux Kernel, Keystone
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
2015-05-29 16:04 ` [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll Murali Karicheri
2015-07-31 14:20 ` Murali Karicheri
@ 2015-07-31 15:30 ` santosh shilimkar
2015-07-31 20:30 ` Olof Johansson
1 sibling, 1 reply; 12+ messages in thread
From: santosh shilimkar @ 2015-07-31 15:30 UTC (permalink / raw
To: mark.rutland, ijc+devicetree, galak, ssantosh, mturquette, sboyd,
devicetree, linux-kernel, linux-clk, arm, olof@lixom.net
Cc: Murali Karicheri, robh+dt, pawel.moll, linux, linux-arm-kernel
Olof,
As discussed patch 1/2 is already made it via clock tree. Please
pick the subject fix for your upcoming fixes pull request.
On 5/29/2015 9:04 AM, Murali Karicheri wrote:
> All of the keystone devices have a separate register to hold post
> divider value for main pll clock. Currently the fixed-postdiv
> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
> use a value of 2 for this. Now that we have fixed this in the pll
> clock driver change the dt bindings for the same.
>
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> ---
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
2015-07-31 14:20 ` Murali Karicheri
@ 2015-07-31 15:30 ` santosh shilimkar
0 siblings, 0 replies; 12+ messages in thread
From: santosh shilimkar @ 2015-07-31 15:30 UTC (permalink / raw
To: Murali Karicheri, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, ssantosh, mturquette, sboyd, devicetree,
linux-kernel, linux-clk, linux, linux-arm-kernel
On 7/31/2015 7:20 AM, Murali Karicheri wrote:
> On 05/29/2015 12:04 PM, Murali Karicheri wrote:
>> All of the keystone devices have a separate register to hold post
>> divider value for main pll clock. Currently the fixed-postdiv
>> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
>> use a value of 2 for this. Now that we have fixed this in the pll
>> clock driver change the dt bindings for the same.
>>
>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
>> ---
[..]
> Santosh,
>
> The clk driver update is already merged to v4.2-rc. Could you send this
> DT update as well for 4.2-rc?
>
Sure.
Regards,
Santosh
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
2015-07-31 15:30 ` santosh shilimkar
@ 2015-07-31 20:30 ` Olof Johansson
2015-07-31 22:06 ` santosh.shilimkar
0 siblings, 1 reply; 12+ messages in thread
From: Olof Johansson @ 2015-07-31 20:30 UTC (permalink / raw
To: santosh shilimkar
Cc: mark.rutland, ijc+devicetree, galak, ssantosh, mturquette, sboyd,
devicetree, linux-kernel, linux-clk, arm, Murali Karicheri,
robh+dt, pawel.moll, linux, linux-arm-kernel
On Fri, Jul 31, 2015 at 08:30:03AM -0700, santosh shilimkar wrote:
> Olof,
>
> As discussed patch 1/2 is already made it via clock tree. Please
> pick the subject fix for your upcoming fixes pull request.
>
> On 5/29/2015 9:04 AM, Murali Karicheri wrote:
> >All of the keystone devices have a separate register to hold post
> >divider value for main pll clock. Currently the fixed-postdiv
> >value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
> >use a value of 2 for this. Now that we have fixed this in the pll
> >clock driver change the dt bindings for the same.
> >
> >Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> >---
> Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
>
>
Thanks, applied.
-Olof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll
2015-07-31 20:30 ` Olof Johansson
@ 2015-07-31 22:06 ` santosh.shilimkar
0 siblings, 0 replies; 12+ messages in thread
From: santosh.shilimkar @ 2015-07-31 22:06 UTC (permalink / raw
To: Olof Johansson
Cc: mark.rutland, ijc+devicetree, galak, ssantosh, mturquette, sboyd,
devicetree, linux-kernel, linux-clk, arm, Murali Karicheri,
robh+dt, pawel.moll, linux, linux-arm-kernel
On 7/31/15 1:30 PM, Olof Johansson wrote:
> On Fri, Jul 31, 2015 at 08:30:03AM -0700, santosh shilimkar wrote:
>> Olof,
>>
>> As discussed patch 1/2 is already made it via clock tree. Please
>> pick the subject fix for your upcoming fixes pull request.
>>
>> On 5/29/2015 9:04 AM, Murali Karicheri wrote:
>>> All of the keystone devices have a separate register to hold post
>>> divider value for main pll clock. Currently the fixed-postdiv
>>> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to
>>> use a value of 2 for this. Now that we have fixed this in the pll
>>> clock driver change the dt bindings for the same.
>>>
>>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
>>> ---
>> Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
>>
>>
>
> Thanks, applied.
>
Thanks Olof !!
Regards,
Santosh
^ permalink raw reply [flat|nested] 12+ messages in thread
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2015-05-29 16:04 [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
[not found] ` <1432915453-409-1-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
2015-05-29 16:04 ` [PATCH 2/2] ARM: dts: keystone: fix dt bindings to use post div register for mainpll Murali Karicheri
2015-07-31 14:20 ` Murali Karicheri
2015-07-31 15:30 ` santosh shilimkar
2015-07-31 15:30 ` santosh shilimkar
2015-07-31 20:30 ` Olof Johansson
2015-07-31 22:06 ` santosh.shilimkar
2015-06-09 15:25 ` [PATCH 1/2] clk: keystone: add support for post divider register for main pll Murali Karicheri
2015-06-15 16:26 ` Murali Karicheri
2015-06-18 22:37 ` Michael Turquette
2015-06-18 22:55 ` santosh shilimkar
[not found] ` <55834C64.6020703-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
2015-06-22 20:15 ` Murali Karicheri
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