From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 062B1149DE2; Thu, 9 May 2024 06:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715235352; cv=none; b=USsY7DKQFcURo9L4Noncsmr/W3/CKqgU/3B1o650HuCyDHKEm1+AWQ2fxSwSqAQSGdgP7er66yjdMw1TrxfEFhjvGUgVOHDNS4QEh1VajywlqsN54eENNdhU1G0tgRorEeyxwpWzamcwlGsGN0YYFxgNln4X358UnxoURlICZ+I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715235352; c=relaxed/simple; bh=G6dU1I9aNo+s1EN/9eYyaLmRUS9K4F18BCgUfTOW2Z4=; h=From:To:Cc:Subject:Date:Message-Id; b=f4WFhZlO1Zmu5x98GYSWKEyPSis7m7OgSTBFCQ3xt5WSC6HStpIKcYJAerq6FI6KGMY9VdfPL6fg7FHUJ12cTLh3jYMA5Ix4D669RzBs9bRPsFpBjWuF2dhxtyJD1V3SE3VObaSAkGsb0rni2h6THIY4OA6j8aB0peX1cTKo/tU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 503171A0BEA; Thu, 9 May 2024 08:15:40 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BCF5B1A1F52; Thu, 9 May 2024 08:15:39 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id C2E81181D0FC; Thu, 9 May 2024 14:15:37 +0800 (+08) From: Richard Zhu To: conor@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, frank.li@nxp.com, conor+dt@kernel.org Cc: hongxing.zhu@nxp.com, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: [PATCH v4 0/3] Add i.MX8Q HSIO PHY support Date: Thu, 9 May 2024 13:56:18 +0800 Message-Id: <1715234181-672-1-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: v4 changes: - Re-format the "phy-cells" as <&hsio_phy lane_id phy_mode controller_id> - Use each lane as a phys entry, suggested by Rob. PCIEA: phys = <&hsio_phy 0 PHY_MODE_PCIE>; or: phys = <&hsio_phy 0 PHY_MODE_PCIE>, <&hsio_phy 1 PHY_MODE_PCIE>; PCIEB: phys = <&hsio_phy 1 PHY_MODE_PCIE>; or: phys = <&hsio_phy 2 PHY_MODE_PCIE>; SATA: phys = <&hsio_phy 2 PHY_MODE_SATA>; - Add a new propery "fsl,hsio-cfg". The HSIO configuration (fsl,hsio-cfg) is one global state. It should be known and used to set global setting: PCIE_AB_SELECT and PHY_X1_EPCS_SEL at the begin of HSIO initialization like this listed below. +-------------------------------------------------------------+ |CRR(SYS.CSR) register|PCIAx2 and|PCIEAx1, PCIEBx1|PCIEAx2 and| | |SATA |SATA |PCIEBx1 | |---------------------|----------|----------------|-----------| |PCIE_AB_SELECT | 0 | 1 | 1 | |---------------------|----------|----------------|-----------| |PHY_X1_EPCS_SEL | 1 | 1 | 0 | +-------------------------------------------------------------+ When first PHY instance is probed, PHY driver can't get a global view of the HSIO use case and doesn't know how to set global setting: PCIE_AB_SELECT and PHYX1_EPCS_SEL. Because first PHY instance doesn't know followed PHY instance use mode. So, one property named "fsl,hsio-cfg" has to be introduced here to specify the setting of the global setting: PCIE_AB_SELECT and PHY_X1_EPCS_SEL. Here is the discussion about this. https://lkml.org/lkml/2024/4/26/231 - Address Conor's comments about the "fsl,refclk-pad-mode". fsl,refclk-pad-mode: description: ... enum: ["input", "output"]. v3:https://patchwork.kernel.org/project/linux-phy/cover/1713939683-15328-1-git-send-email-hongxing.zhu@nxp.com/ v3 changes: Refer to Conor's comments. - Let filename match a compatible - Refine description of the fsl,refclk-pad-mode. - Remove power-domains description. - Keep clock ording for two devices. - Drop the unused label and status. Refer to Rob's comments. - Use standard phy mode defines. - Correct the spell mistakes in the binding document. v2:https://patchwork.kernel.org/project/linux-phy/cover/1712036704-21064-1-git-send-email-hongxing.zhu@nxp.com/ v2 changes: - Place the dt-bindings header file changes as the first one in the patch-set, make the annotation more clear, and add Frank's Reviewed-by tag. v1:https://patchwork.kernel.org/project/linux-phy/cover/1711699790-16494-1-git-send-email-hongxing.zhu@nxp.com/ [PATCH v4 1/3] dt-bindings: phy: phy-imx8-pcie: Add header file for [PATCH v4 2/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding [PATCH v4 3/3] phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml | 142 ++++++++++++++++++++ drivers/phy/freescale/Kconfig | 8 ++ drivers/phy/freescale/Makefile | 1 + drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 598 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/dt-bindings/phy/phy-imx8-pcie.h | 29 +++++ 5 files changed, 778 insertions(+)