* [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2
@ 2023-06-20 9:51 AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property AngeloGioacchino Del Regno
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel
This series adds support for handling "v2" firmware's IOMMU, found
on at least MSM8956 and MSM8976 (some other SoCs also need the same
but I honestly don't remember which ones precisely).
This is strictly required to get functional IOMMUs on these SoCs.
I'm sorry for not performing a much needed schema conversion on
qcom,iommu.txt, but I really didn't have time to do that :-(
This series was tested on Sony Xperia X and X Compact (MSM8956):
ADSP, LPASS, Venus, MSS, MDP and GPU are happy :-)
Changes in v4:
- Rebase over next-20230619
- Rewrite qcom,iommu.txt changes to qcom,iommu.yaml
- Changed reset writes to only disable CB through CB_SCTLR
and reset CB_FSR and CB_FAR
- Addressed misc reviewer's comments
Changes in v3:
- Removed useless FSRRESTORE reset and definition as pointed
out in Robin Murphy's review
- Fixed qcom,iommu.txt changes: squashed MSM8976 compatible
string addition with msm-iommu-v2 generics addition
Changes in v2:
- Added back Marijn's notes (sorry man!)
- Added ARM_SMMU_CB_FSRRESTORE definition
- Changed context bank reset to properly set FSR and FSRRESTORE
AngeloGioacchino Del Regno (6):
dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property
iommu/qcom: Use the asid read from device-tree if specified
iommu/qcom: Disable and reset context bank before programming
iommu/qcom: Index contexts by asid number to allow asid 0
dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles
iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts
.../devicetree/bindings/iommu/qcom,iommu.yaml | 22 +++++--
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 62 ++++++++++++++-----
2 files changed, 64 insertions(+), 20 deletions(-)
--
2.40.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
@ 2023-06-20 9:51 ` AngeloGioacchino Del Regno
2023-06-22 1:50 ` Rob Herring
2023-06-20 9:51 ` [PATCH v4 2/6] iommu/qcom: Use the asid read from device-tree if specified AngeloGioacchino Del Regno
` (4 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel
Add a new "qcom,ctx-num" property to force an ASID number on IOMMU
contexts where required.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
index d9fabdf930d9..0446ccc4116e 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
@@ -71,6 +71,11 @@ patternProperties:
reg:
maxItems: 1
+ qcom,ctx-num:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The ASID number associated to the context bank.
+
required:
- compatible
- interrupts
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 2/6] iommu/qcom: Use the asid read from device-tree if specified
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property AngeloGioacchino Del Regno
@ 2023-06-20 9:51 ` AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 3/6] iommu/qcom: Disable and reset context bank before programming AngeloGioacchino Del Regno
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel,
Marijn Suijten
As specified in this driver, the context banks are 0x1000 apart but
on some SoCs the context number does not necessarily match this
logic, hence we end up using the wrong ASID: keeping in mind that
this IOMMU implementation relies heavily on SCM (TZ) calls, it is
mandatory that we communicate the right context number.
Since this is all about how context banks are mapped in firmware,
which may be board dependent (as a different firmware version may
eventually change the expected context bank numbers), introduce a
new property "qcom,ctx-num": when found, the ASID will be forced
as read from the devicetree.
When "qcom,ctx-num" is not found, this driver retains the previous
behavior as to avoid breaking older devicetrees or systems that do
not require forcing ASID numbers.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
[Marijn: Rebased over next-20221111]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index a503ed758ec3..b661b559ea01 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -531,7 +531,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
* index into qcom_iommu->ctxs:
*/
if (WARN_ON(asid < 1) ||
- WARN_ON(asid > qcom_iommu->num_ctxs)) {
+ WARN_ON(asid > qcom_iommu->num_ctxs) ||
+ WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) {
put_device(&iommu_pdev->dev);
return -EINVAL;
}
@@ -617,7 +618,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev)
static int get_asid(const struct device_node *np)
{
- u32 reg;
+ u32 reg, val;
+ int asid;
/* read the "reg" property directly to get the relative address
* of the context bank, and calculate the asid from that:
@@ -625,7 +627,17 @@ static int get_asid(const struct device_node *np)
if (of_property_read_u32_index(np, "reg", 0, ®))
return -ENODEV;
- return reg / 0x1000; /* context banks are 0x1000 apart */
+ /*
+ * Context banks are 0x1000 apart but, in some cases, the ASID
+ * number doesn't match to this logic and needs to be passed
+ * from the DT configuration explicitly.
+ */
+ if (!of_property_read_u32(np, "qcom,ctx-num", &val))
+ asid = val;
+ else
+ asid = reg / 0x1000;
+
+ return asid;
}
static int qcom_iommu_ctx_probe(struct platform_device *pdev)
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 3/6] iommu/qcom: Disable and reset context bank before programming
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 2/6] iommu/qcom: Use the asid read from device-tree if specified AngeloGioacchino Del Regno
@ 2023-06-20 9:51 ` AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 4/6] iommu/qcom: Index contexts by asid number to allow asid 0 AngeloGioacchino Del Regno
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel
Writing the new TTBRs, TCRs and MAIRs on a previously enabled
context bank may trigger a context fault, resulting in firmware
driven AP resets: change the domain initialization programming
sequence to disable the context bank(s) and to also clear the
related fault address (CB_FAR) and fault status (CB_FSR)
registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1.
Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index b661b559ea01..8b48f7e8f3db 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
ctx->secure_init = true;
}
+ /* Disable context bank before programming */
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+
+ /* Clear context bank fault address fault status registers */
+ iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
+
/* TTBRs */
iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 4/6] iommu/qcom: Index contexts by asid number to allow asid 0
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
` (2 preceding siblings ...)
2023-06-20 9:51 ` [PATCH v4 3/6] iommu/qcom: Disable and reset context bank before programming AngeloGioacchino Del Regno
@ 2023-06-20 9:51 ` AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 6/6] iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts AngeloGioacchino Del Regno
5 siblings, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel
This driver was indexing the contexts by asid-1, which is probably
done under the assumption that the first ASID is always 1.
Unfortunately this is not always true: at least for MSM8956 and
MSM8976's GPU IOMMU, the gpu_user context's ASID number is zero.
To allow using a zero asid number, index the contexts by `asid`
instead of by `asid - 1`.
While at it, also enhance human readability by renaming the
`num_ctxs` member of struct qcom_iommu_dev to `max_asid`.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 8b48f7e8f3db..f4b948a0bd1c 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -51,8 +51,8 @@ struct qcom_iommu_dev {
struct clk_bulk_data clks[CLK_NUM];
void __iomem *local_base;
u32 sec_id;
- u8 num_ctxs;
- struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
+ u8 max_asid;
+ struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */
};
struct qcom_iommu_ctx {
@@ -94,7 +94,7 @@ static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid
struct qcom_iommu_dev *qcom_iommu = d->iommu;
if (!qcom_iommu)
return NULL;
- return qcom_iommu->ctxs[asid - 1];
+ return qcom_iommu->ctxs[asid];
}
static inline void
@@ -534,12 +534,10 @@ static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
qcom_iommu = platform_get_drvdata(iommu_pdev);
/* make sure the asid specified in dt is valid, so we don't have
- * to sanity check this elsewhere, since 'asid - 1' is used to
- * index into qcom_iommu->ctxs:
+ * to sanity check this elsewhere:
*/
- if (WARN_ON(asid < 1) ||
- WARN_ON(asid > qcom_iommu->num_ctxs) ||
- WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) {
+ if (WARN_ON(asid > qcom_iommu->max_asid) ||
+ WARN_ON(qcom_iommu->ctxs[asid] == NULL)) {
put_device(&iommu_pdev->dev);
return -EINVAL;
}
@@ -696,7 +694,7 @@ static int qcom_iommu_ctx_probe(struct platform_device *pdev)
dev_dbg(dev, "found asid %u\n", ctx->asid);
- qcom_iommu->ctxs[ctx->asid - 1] = ctx;
+ qcom_iommu->ctxs[ctx->asid] = ctx;
return 0;
}
@@ -708,7 +706,7 @@ static void qcom_iommu_ctx_remove(struct platform_device *pdev)
platform_set_drvdata(pdev, NULL);
- qcom_iommu->ctxs[ctx->asid - 1] = NULL;
+ qcom_iommu->ctxs[ctx->asid] = NULL;
}
static const struct of_device_id ctx_of_match[] = {
@@ -755,11 +753,11 @@ static int qcom_iommu_device_probe(struct platform_device *pdev)
for_each_child_of_node(dev->of_node, child)
max_asid = max(max_asid, get_asid(child));
- qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid),
+ qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid + 1),
GFP_KERNEL);
if (!qcom_iommu)
return -ENOMEM;
- qcom_iommu->num_ctxs = max_asid;
+ qcom_iommu->max_asid = max_asid;
qcom_iommu->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
` (3 preceding siblings ...)
2023-06-20 9:51 ` [PATCH v4 4/6] iommu/qcom: Index contexts by asid number to allow asid 0 AngeloGioacchino Del Regno
@ 2023-06-20 9:51 ` AngeloGioacchino Del Regno
2023-06-22 1:51 ` Rob Herring
2023-06-20 9:51 ` [PATCH v4 6/6] iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts AngeloGioacchino Del Regno
5 siblings, 1 reply; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel
Add compatible string "qcom,msm-iommu-v2" for the inner node,
along with "qcom,msm8976-iommu" as a first user of it and
"qcom,msm-iommu-v2-ns" and "qcom,msm-iommu-v2-sec" for the context
bank nodes to support Qualcomm's secure fw "SMMU v2" implementation.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/iommu/qcom,iommu.yaml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
index 0446ccc4116e..b94dbab1e1f1 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
@@ -17,11 +17,16 @@ description: |
properties:
compatible:
- items:
- - enum:
- - qcom,msm8916-iommu
- - qcom,msm8953-iommu
- - const: qcom,msm-iommu-v1
+ oneOf:
+ - items:
+ - enum:
+ - qcom,msm8916-iommu
+ - qcom,msm8953-iommu
+ - const: qcom,msm-iommu-v1
+ - items:
+ - enum:
+ - qcom,msm8976-iommu
+ - const: qcom,msm-iommu-v2
clocks:
items:
@@ -64,6 +69,8 @@ patternProperties:
enum:
- qcom,msm-iommu-v1-ns
- qcom,msm-iommu-v1-sec
+ - qcom,msm-iommu-v2-ns
+ - qcom,msm-iommu-v2-sec
interrupts:
maxItems: 1
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v4 6/6] iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
` (4 preceding siblings ...)
2023-06-20 9:51 ` [PATCH v4 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles AngeloGioacchino Del Regno
@ 2023-06-20 9:51 ` AngeloGioacchino Del Regno
5 siblings, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-06-20 9:51 UTC (permalink / raw
To: agross
Cc: andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski+dt, conor+dt,
robdclark, linux-arm-msm, iommu, devicetree, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, kernel,
Marijn Suijten
On some SoCs like MSM8956, MSM8976 and others, secure contexts are
also secured: these get programmed by the bootloader or TZ (as usual)
but their "interesting" registers are locked out by the hypervisor,
disallowing direct register writes from Linux and, in many cases,
completely disallowing the reprogramming of TTBR, TCR, MAIR and other
registers including, but not limited to, resetting contexts.
This is referred downstream as a "v2" IOMMU but this is effectively
a "v2 firmware configuration" instead.
Luckily, the described behavior of version 2 is effective only on
secure contexts and not on non-secure ones: add support for that,
finally getting a completely working IOMMU on at least MSM8956/76.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
[Marijn: Rebased over next-20221111]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index f4b948a0bd1c..5b69f336b797 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -59,6 +59,7 @@ struct qcom_iommu_ctx {
struct device *dev;
void __iomem *base;
bool secure_init;
+ bool secured_ctx;
u8 asid; /* asid and ctx bank # are 1:1 */
struct iommu_domain *domain;
};
@@ -273,6 +274,12 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
ctx->secure_init = true;
}
+ /* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */
+ if (ctx->secured_ctx) {
+ ctx->domain = domain;
+ continue;
+ }
+
/* Disable context bank before programming */
iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
@@ -669,10 +676,14 @@ static int qcom_iommu_ctx_probe(struct platform_device *pdev)
if (irq < 0)
return -ENODEV;
+ if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec"))
+ ctx->secured_ctx = true;
+
/* clear IRQs before registering fault handler, just in case the
* boot-loader left us a surprise:
*/
- iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
+ if (!ctx->secured_ctx)
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
ret = devm_request_irq(dev, irq,
qcom_iommu_fault,
@@ -712,6 +723,8 @@ static void qcom_iommu_ctx_remove(struct platform_device *pdev)
static const struct of_device_id ctx_of_match[] = {
{ .compatible = "qcom,msm-iommu-v1-ns" },
{ .compatible = "qcom,msm-iommu-v1-sec" },
+ { .compatible = "qcom,msm-iommu-v2-ns" },
+ { .compatible = "qcom,msm-iommu-v2-sec" },
{ /* sentinel */ }
};
@@ -729,7 +742,8 @@ static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
struct device_node *child;
for_each_child_of_node(qcom_iommu->dev->of_node, child) {
- if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) {
+ if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") ||
+ of_device_is_compatible(child, "qcom,msm-iommu-v2-sec")) {
of_node_put(child);
return true;
}
@@ -873,6 +887,7 @@ static const struct dev_pm_ops qcom_iommu_pm_ops = {
static const struct of_device_id qcom_iommu_of_match[] = {
{ .compatible = "qcom,msm-iommu-v1" },
+ { .compatible = "qcom,msm-iommu-v2" },
{ /* sentinel */ }
};
--
2.40.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property
2023-06-20 9:51 ` [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property AngeloGioacchino Del Regno
@ 2023-06-22 1:50 ` Rob Herring
0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2023-06-22 1:50 UTC (permalink / raw
To: AngeloGioacchino Del Regno
Cc: agross, andersson, konrad.dybcio, dmitry.baryshkov, joro, will,
robin.murphy, krzysztof.kozlowski+dt, conor+dt, robdclark,
linux-arm-msm, iommu, devicetree, linux-kernel, linux-arm-kernel,
kernel
On Tue, Jun 20, 2023 at 11:51:22AM +0200, AngeloGioacchino Del Regno wrote:
> Add a new "qcom,ctx-num" property to force an ASID number on IOMMU
> contexts where required.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> Documentation/devicetree/bindings/iommu/qcom,iommu.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> index d9fabdf930d9..0446ccc4116e 100644
> --- a/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml
> @@ -71,6 +71,11 @@ patternProperties:
> reg:
> maxItems: 1
>
> + qcom,ctx-num:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + The ASID number associated to the context bank.
If the value is ASID, then qcom,ctx-asid would be more descriptive.
> +
> required:
> - compatible
> - interrupts
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles
2023-06-20 9:51 ` [PATCH v4 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles AngeloGioacchino Del Regno
@ 2023-06-22 1:51 ` Rob Herring
0 siblings, 0 replies; 9+ messages in thread
From: Rob Herring @ 2023-06-22 1:51 UTC (permalink / raw
To: AngeloGioacchino Del Regno
Cc: will, robdclark, linux-arm-kernel, conor+dt, robin.murphy, agross,
iommu, dmitry.baryshkov, konrad.dybcio, linux-arm-msm, andersson,
joro, devicetree, robh+dt, krzysztof.kozlowski+dt, kernel,
linux-kernel
On Tue, 20 Jun 2023 11:51:26 +0200, AngeloGioacchino Del Regno wrote:
> Add compatible string "qcom,msm-iommu-v2" for the inner node,
> along with "qcom,msm8976-iommu" as a first user of it and
> "qcom,msm-iommu-v2-ns" and "qcom,msm-iommu-v2-sec" for the context
> bank nodes to support Qualcomm's secure fw "SMMU v2" implementation.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../devicetree/bindings/iommu/qcom,iommu.yaml | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-06-22 1:51 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-20 9:51 [PATCH v4 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-num property AngeloGioacchino Del Regno
2023-06-22 1:50 ` Rob Herring
2023-06-20 9:51 ` [PATCH v4 2/6] iommu/qcom: Use the asid read from device-tree if specified AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 3/6] iommu/qcom: Disable and reset context bank before programming AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 4/6] iommu/qcom: Index contexts by asid number to allow asid 0 AngeloGioacchino Del Regno
2023-06-20 9:51 ` [PATCH v4 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles AngeloGioacchino Del Regno
2023-06-22 1:51 ` Rob Herring
2023-06-20 9:51 ` [PATCH v4 6/6] iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts AngeloGioacchino Del Regno
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