From: Xianwei Zhao <xianwei.zhao@amlogic.com>
To: <linux-amlogic@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Xianwei Zhao <xianwei.zhao@amlogic.com>
Subject: [PATCH v8 0/5] Add C3 SoC PLLs and Peripheral clock
Date: Tue, 30 Apr 2024 14:44:33 +0800 [thread overview]
Message-ID: <20240430064438.2094701-1-xianwei.zhao@amlogic.com> (raw)
Changes since V7 [1]:
- Remove included head file not used.
- Link to v7: https://lore.kernel.org/all/20240424050928.1997820-1-xianwei.zhao@amlogic.com
Changes since V6 [12]:
- Add pad src for rtc clock.
- Add SCMI clock controller support, move some clock node in SCMI,such as GP1 PLL DDR USB etc.
- Fix some spelling mistake.
- Use lower case for bindings and update some input clocks desc.
- Update some clock comments.
- Delete prefix "AML_" for macro definition.
- Addd some clock annotation and some clock flag CRITICAL.
- Add maximum for regmap_config.
- Delete some unused register definition and unused clock inputs.
- Drop patch subject redundant "bindings". Suggested by Krzysztof.
- Not reference header file "clk.h" and replace comment. Suggested by Jerome.
- Modify description about board in Kconfig file help item. Suggested by Jerome.
- Link to v6: https://lore.kernel.org/all/20231106085554.3237511-1-xianwei.zhao@amlogic.com
Changes since V5 [3]:
- Fix some typo and modify formart for MARCO. Suggested by Jerome.
- Add pad clock for peripheral input clock in bindings.
- Add some description for explaining why ddr_dpll_pt_clk and cts_msr_clk are out of tree.
Changes since V4 [10]:
- Change some fw_name of clocks. Suggested by Jerome.
- Delete minItem of clocks.
- Add CLk_GET_RATE_NOCACHE flags for gp1_pll
- Fix some format. and fix width as 8 for mclk_pll_dco.
- exchange gate and divder for fclk_50m clock.
- add CLK_SET_RATE_PARENT for axi_a_divder & axi_b_divder.
- add CLK_IS_CRITICAL for axi_clk
- Optimized macro define for pwm clk.
- add cts_oscin_clk mux between 24M and 32k
- add some missing gate clock, such as ddr_pll.
Changes since V3 [7]:
- Modify Kconfig desc and PLL yaml clk desc.
- Fix some format.Suggested by Yixun and Jerome.
- Add flag CLK_GET_RATE_NOCACHE for sys_clk.
- Optimized macro define for pwm clk.
- Use flag CLK_IS_CRITICAL for axi_clk.
- Add some description for some clocks.
- Use FCLK_50M instead of FCLK_DIV40.
Changes since V2 [4]:
- Modify some format, include clk name & inline, and so on.
- Define marco for pwm clock.
- Add GP1_PLL clock.
- Modify yaml use raw instead of macro.
Changes since V1 [2]:
- Fix errors when check binding by using "make dt_binding_check".
- Delete macro definition.
Xianwei Zhao (5):
dt-bindings: clock: add Amlogic C3 PLL clock controller
dt-bindings: clock: add Amlogic C3 SCMI clock controller support
dt-bindings: clock: add Amlogic C3 peripherals clock controller
clk: meson: c3: add support for the C3 SoC PLL clock
clk: meson: c3: add c3 clock peripherals controller driver
.../clock/amlogic,c3-peripherals-clkc.yaml | 120 +
.../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +
drivers/clk/meson/Kconfig | 29 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/c3-peripherals.c | 2365 +++++++++++++++++
drivers/clk/meson/c3-pll.c | 746 ++++++
.../clock/amlogic,c3-peripherals-clkc.h | 212 ++
.../dt-bindings/clock/amlogic,c3-pll-clkc.h | 40 +
.../dt-bindings/clock/amlogic,c3-scmi-clkc.h | 27 +
9 files changed, 3600 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
create mode 100644 drivers/clk/meson/c3-peripherals.c
create mode 100644 drivers/clk/meson/c3-pll.c
create mode 100644 include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,c3-scmi-clkc.h
base-commit: ba535bce57e71463a86f8b33a0ea88c26e3a6418
--
2.39.2
next reply other threads:[~2024-04-30 6:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 6:44 Xianwei Zhao [this message]
2024-04-30 6:44 ` [PATCH v8 1/5] dt-bindings: clock: add Amlogic C3 PLL clock controller Xianwei Zhao
2024-04-30 6:44 ` [PATCH v8 2/5] dt-bindings: clock: add Amlogic C3 SCMI clock controller support Xianwei Zhao
2024-04-30 6:44 ` [PATCH v8 3/5] dt-bindings: clock: add Amlogic C3 peripherals clock controller Xianwei Zhao
2024-04-30 6:44 ` [PATCH v8 4/5] clk: meson: c3: add support for the C3 SoC PLL clock Xianwei Zhao
2024-05-03 14:11 ` Jerome Brunet
2024-05-08 8:06 ` Xianwei Zhao
2024-04-30 6:44 ` [PATCH v8 5/5] clk: meson: c3: add c3 clock peripherals controller driver Xianwei Zhao
2024-05-03 14:04 ` Jerome Brunet
2024-05-08 8:08 ` Xianwei Zhao
2024-05-03 14:12 ` [PATCH v8 0/5] Add C3 SoC PLLs and Peripheral clock Jerome Brunet
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240430064438.2094701-1-xianwei.zhao@amlogic.com \
--to=xianwei.zhao@amlogic.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jbrunet@baylibre.com \
--cc=khilman@baylibre.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-amlogic@lists.infradead.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=neil.armstrong@linaro.org \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).