From: Rob Herring <robh@kernel.org>
To: Sean Anderson <sean.anderson@linux.dev>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, "Michal Simek" <michal.simek@amd.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Thippeswamy Havalige" <thippeswamy.havalige@amd.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
"Conor Dooley" <conor+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys
Date: Tue, 7 May 2024 15:06:40 -0500 [thread overview]
Message-ID: <20240507200640.GA955773-robh@kernel.org> (raw)
In-Reply-To: <20240506161510.2841755-2-sean.anderson@linux.dev>
On Mon, May 06, 2024 at 12:15:04PM -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
>
> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
> ---
>
> Changes in v2:
> - Remove phy-names
> - Add an example
>
> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 426f90a47f35..693b29039a9b 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -61,6 +61,10 @@ properties:
> interrupt-map:
> maxItems: 4
>
> + phys:
> + minItems: 1
> + maxItems: 4
I assume this is 1 phy per lane, but don't make me assume and define it.
Rob
next prev parent reply other threads:[~2024-05-07 20:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-06 16:15 [PATCH v2 0/7] PCI: xilinx-nwl: Add phy support Sean Anderson
2024-05-06 16:15 ` [PATCH v2 1/7] dt-bindings: pci: xilinx-nwl: Add phys Sean Anderson
2024-05-07 20:06 ` Rob Herring [this message]
2024-05-07 20:07 ` Sean Anderson
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