From: Niklas Cassel <cassel@kernel.org>
To: "Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>,
"Niklas Cassel" <cassel@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Damien Le Moal" <dlemoal@kernel.org>,
"Jon Lin" <jon.lin@rock-chips.com>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Simon Xue" <xxm@rock-chips.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org
Subject: [PATCH v3 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode
Date: Wed, 08 May 2024 15:13:44 +0200 [thread overview]
Message-ID: <20240508-rockchip-pcie-ep-v1-v3-13-1748e202b084@kernel.org> (raw)
In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org>
Add rock5b overlays for PCIe endpoint mode support.
If using the rock5b as an endpoint against a normal PC, only the
rk3588-rock-5b-pcie-ep.dtbo needs to be applied.
If using two rock5b:s, with one board as EP and the other board as RC,
rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to
be applied to the respective boards.
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
arch/arm64/boot/dts/rockchip/Makefile | 5 +++++
.../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++
.../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++
3 files changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index f906a868b71a..d827432d5111 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
@@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+
+# Enable support for device-tree overlays
+DTC_FLAGS_rk3588-rock-5b += -@
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso
new file mode 100644
index 000000000000..672d748fcc67
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
+ * in the SRNS (Separate Reference Clock No Spread) configuration.
+ *
+ * NOTE: If using a setup with two ROCK 5B:s, with one board running in
+ * RC mode and the other board running in EP mode, see also the device
+ * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie30phy {
+ rockchip,rx-common-refclk-mode = <0 0 0 0>;
+};
+
+&pcie3x4 {
+ status = "disabled";
+};
+
+&pcie3x4_ep {
+ vpcie3v3-supply = <&vcc3v3_pcie30>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso
new file mode 100644
index 000000000000..1a0f1af65c43
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex
+ * mode in the SRNS (Separate Reference Clock No Spread) configuration.
+ *
+ * This device tree overlay is only needed (on the RC side) when running
+ * a setup with two ROCK 5B:s, with one board running in RC mode and the
+ * other board running in EP mode.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&pcie30phy {
+ rockchip,rx-common-refclk-mode = <0 0 0 0>;
+};
--
2.44.0
prev parent reply other threads:[~2024-05-08 13:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-08 13:13 [PATCH v3 00/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 01/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 02/13] dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 03/13] dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy irqs Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 04/13] dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 05/13] dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy irq Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 06/13] dt-bindings: rockchip: Add DesignWare based PCIe Endpoint controller Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 07/13] PCI: dw-rockchip: Fix weird indentation Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 08/13] PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 09/13] PCI: dw-rockchip: Refactor the driver to prepare for EP mode Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 10/13] PCI: dw-rockchip: Add endpoint mode support Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 11/13] misc: pci_endpoint_test: Add support for rockchip rk3588 Niklas Cassel
2024-05-08 13:13 ` [PATCH v3 12/13] arm64: dts: rockchip: Add PCIe endpoint mode support Niklas Cassel
2024-05-08 13:13 ` Niklas Cassel [this message]
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