From: Mayank Rana <quic_mrana@quicinc.com>
To: "Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
johan+linaro@kernel.org, bmasney@redhat.com, djakov@kernel.org
Cc: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<vireshk@kernel.org>, <quic_vbadigan@quicinc.com>,
<quic_skananth@quicinc.com>, <quic_nitegupt@quicinc.com>,
<quic_parass@quicinc.com>, <krzysztof.kozlowski@linaro.org>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Subject: Re: [PATCH v12 2/6] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path
Date: Thu, 9 May 2024 11:34:31 -0700 [thread overview]
Message-ID: <60e92614-5e56-46c4-ab4f-1f0261a3a9ab@quicinc.com> (raw)
In-Reply-To: <20240427-opp_support-v12-2-f6beb0a1f2fc@quicinc.com>
Hi Krishna
On 4/26/2024 6:52 PM, Krishna chaitanya chundru wrote:
> To access the host controller registers of the host controller and the
> endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should
> be voted otherwise it may lead to NoC (Network on chip) timeout.
> We are surviving because of other driver voting for this path.
>
> As there is less access on this path compared to PCIe to mem path
> add minimum vote i.e 1KBps bandwidth always which is sufficient enough
> to keep the path active and is recommended by HW team.
>
> During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while
> disabling the boot CPU). So do not disable the CPU-PCIe interconnect path
> during S2RAM as that may lead to NoC error.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 44 ++++++++++++++++++++++++++++++----
> 1 file changed, 40 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 14772edcf0d3..465d63b4be1c 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -245,6 +245,7 @@ struct qcom_pcie {
> struct phy *phy;
> struct gpio_desc *reset;
> struct icc_path *icc_mem;
> + struct icc_path *icc_cpu;
> const struct qcom_pcie_cfg *cfg;
> struct dentry *debugfs;
> bool suspended;
> @@ -1409,6 +1410,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
> if (IS_ERR(pcie->icc_mem))
> return PTR_ERR(pcie->icc_mem);
>
> + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie");
> + if (IS_ERR(pcie->icc_cpu))
> + return PTR_ERR(pcie->icc_cpu);
> /*
> * Some Qualcomm platforms require interconnect bandwidth constraints
> * to be set before enabling interconnect clocks.
> @@ -1418,7 +1422,20 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
> */
> ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
> if (ret) {
> - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
> + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
> + ret);
> + return ret;
> + }
> +
> + /*
> + * Since the CPU-PCIe path is only used for activities like register
> + * access of the host controller and endpoint Config/BAR space access,
> + * HW team has recommended to use a minimal bandwidth of 1KBps just to
> + * keep the path active.
> + */
> + ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1));
> + if (ret) {
> + dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n",
> ret);
Is it needed to undo icc_mem related bus bandwidth vote here ?
> return ret;
> }
> @@ -1448,7 +1465,7 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
>
> ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
> if (ret) {
> - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
> + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
> ret);
> }
> }
next prev parent reply other threads:[~2024-05-09 18:34 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-27 1:52 [PATCH v12 0/6] PCI: qcom: Add support for OPP Krishna chaitanya chundru
2024-04-27 1:52 ` [PATCH v12 1/6] arm64: dts: qcom: sm8450: Add interconnect path to PCIe node Krishna chaitanya chundru
2024-04-27 1:52 ` [PATCH v12 2/6] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path Krishna chaitanya chundru
2024-04-30 5:21 ` Manivannan Sadhasivam
2024-05-09 18:34 ` Mayank Rana [this message]
2024-05-14 9:37 ` Krishna Chaitanya Chundru
2024-04-27 1:52 ` [PATCH v12 3/6] dt-bindings: pci: qcom: Add OPP table Krishna chaitanya chundru
2024-04-27 1:52 ` [PATCH v12 4/6] arm64: dts: qcom: sm8450: Add OPP table support to PCIe Krishna chaitanya chundru
2024-04-27 1:52 ` [PATCH v12 5/6] PCI: Bring the PCIe speed to MBps logic to new pcie_link_speed_to_mbps() Krishna chaitanya chundru
2024-04-27 1:52 ` [PATCH v12 6/6] PCI: qcom: Add OPP support to scale performance Krishna chaitanya chundru
2024-04-30 5:26 ` Manivannan Sadhasivam
2024-05-09 15:51 ` Krishna Chaitanya Chundru
2024-05-14 9:28 ` Manivannan Sadhasivam
2024-05-14 9:35 ` Krishna Chaitanya Chundru
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=60e92614-5e56-46c4-ab4f-1f0261a3a9ab@quicinc.com \
--to=quic_mrana@quicinc.com \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=bmasney@redhat.com \
--cc=bryan.odonoghue@linaro.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=djakov@kernel.org \
--cc=johan+linaro@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=quic_krichai@quicinc.com \
--cc=quic_nitegupt@quicinc.com \
--cc=quic_parass@quicinc.com \
--cc=quic_skananth@quicinc.com \
--cc=quic_vbadigan@quicinc.com \
--cc=robh@kernel.org \
--cc=vireshk@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).