From: Charlie Jenkins <charlie@rivosinc.com>
To: "Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Guo Ren" <guoren@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@csie.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Palmer Dabbelt <palmer@rivosinc.com>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH v6 03/17] riscv: vector: Use vlenb from DT
Date: Fri, 03 May 2024 11:18:18 -0700 [thread overview]
Message-ID: <20240503-dev-charlie-support_thead_vector_6_9-v6-3-cb7624e65d82@rivosinc.com> (raw)
In-Reply-To: <20240503-dev-charlie-support_thead_vector_6_9-v6-0-cb7624e65d82@rivosinc.com>
If vlenb is provided in the device tree, prefer that over reading the
vlenb csr.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
arch/riscv/include/asm/cpufeature.h | 2 ++
arch/riscv/kernel/cpufeature.c | 47 +++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/vector.c | 12 +++++++++-
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 347805446151..0c4f08577015 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
/* Per-cpu ISA extensions. */
extern struct riscv_isainfo hart_isa[NR_CPUS];
+extern u32 riscv_vlenb_of;
+
void riscv_user_isa_enable(void);
#if defined(CONFIG_RISCV_MISALIGNED)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3ed2359eae35..6c143ea9592b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
/* Per-cpu ISA extensions. */
struct riscv_isainfo hart_isa[NR_CPUS];
+u32 riscv_vlenb_of;
+
/**
* riscv_isa_extension_base() - Get base extension word
*
@@ -648,6 +650,46 @@ static int __init riscv_isa_fallback_setup(char *__unused)
early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
#endif
+static int has_riscv_homogeneous_vlenb(void)
+{
+ int cpu;
+ u32 prev_vlenb = 0;
+ u32 vlenb;
+
+ /* Ignore vlenb if vector is not enabled in the kernel */
+ if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
+ return 0;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *cpu_node;
+
+ cpu_node = of_cpu_device_node_get(cpu);
+ if (!cpu_node) {
+ pr_warn("Unable to find cpu node\n");
+ return -ENOENT;
+ }
+
+ if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) {
+ of_node_put(cpu_node);
+
+ if (prev_vlenb)
+ return -ENOENT;
+ continue;
+ }
+
+ if (prev_vlenb && vlenb != prev_vlenb) {
+ of_node_put(cpu_node);
+ return -ENOENT;
+ }
+
+ prev_vlenb = vlenb;
+ of_node_put(cpu_node);
+ }
+
+ riscv_vlenb_of = vlenb;
+ return 0;
+}
+
void __init riscv_fill_hwcap(void)
{
char print_str[NUM_ALPHA_EXTS + 1];
@@ -671,6 +713,11 @@ void __init riscv_fill_hwcap(void)
pr_info("Falling back to deprecated \"riscv,isa\"\n");
riscv_fill_hwcap_from_isa_string(isa2hwcap);
}
+
+ if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) {
+ pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n");
+ elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
+ }
}
/*
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 6727d1d3b8f2..e04586cdb7f0 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void)
{
unsigned long this_vsize;
- /* There are 32 vector registers with vlenb length. */
+ /*
+ * There are 32 vector registers with vlenb length.
+ *
+ * If the riscv,vlenb property was provided by the firmware, use that
+ * instead of probing the CSRs.
+ */
+ if (riscv_vlenb_of) {
+ this_vsize = riscv_vlenb_of * 32;
+ return 0;
+ }
+
riscv_v_enable();
this_vsize = csr_read(CSR_VLENB) * 32;
riscv_v_disable();
--
2.44.0
next prev parent reply other threads:[~2024-05-03 18:18 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-03 18:18 [PATCH v6 00/17] riscv: Support vendor extensions and xtheadvector Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 01/17] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-05-16 12:48 ` Andy Chiu
2024-05-03 18:18 ` [PATCH v6 02/17] dt-bindings: riscv: cpus: add a vlen register length property Charlie Jenkins
2024-05-16 12:50 ` Andy Chiu
2024-05-03 18:18 ` Charlie Jenkins [this message]
2024-05-09 8:17 ` [PATCH v6 03/17] riscv: vector: Use vlenb from DT Conor Dooley
2024-05-16 13:11 ` Andy Chiu
2024-05-16 14:00 ` Andy Chiu
2024-05-16 16:24 ` Conor Dooley
2024-05-16 20:28 ` Charlie Jenkins
2024-05-16 20:31 ` Conor Dooley
2024-05-03 18:18 ` [PATCH v6 04/17] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 05/17] riscv: Extend cpufeature.c to detect vendor extensions Charlie Jenkins
2024-05-03 21:02 ` Evan Green
2024-05-09 8:18 ` Conor Dooley
2024-05-03 18:18 ` [PATCH v6 06/17] riscv: Add vendor extensions to /proc/cpuinfo Charlie Jenkins
2024-05-03 21:03 ` Evan Green
2024-05-07 17:03 ` Conor Dooley
2024-05-10 20:50 ` Conor Dooley
2024-05-10 21:25 ` Charlie Jenkins
2024-05-10 21:32 ` Conor Dooley
2024-05-10 21:47 ` Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 07/17] riscv: Introduce vendor variants of extension helpers Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 08/17] riscv: cpufeature: Extract common elements from extension checking Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 09/17] riscv: Convert xandespmu to use the vendor extension framework Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 10/17] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 11/17] riscv: csr: Add CSR encodings for VCSR_VXRM/VCSR_VXSAT Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 12/17] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 13/17] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-05-13 8:45 ` Andy Chiu
2024-05-13 16:56 ` Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 14/17] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 15/17] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 16/17] selftests: riscv: Fix vector tests Charlie Jenkins
2024-05-03 18:18 ` [PATCH v6 17/17] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-05-07 17:21 ` [PATCH v6 00/17] riscv: Support vendor extensions and xtheadvector Conor Dooley
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