From: "Clément Léger" <cleger@rivosinc.com>
To: Conor Dooley <conor@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Anup Patel <anup@brainfault.org>, Shuah Khan <shuah@kernel.org>,
Atish Patra <atishp@atishpatra.org>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 04/12] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb
Date: Mon, 22 Apr 2024 10:53:10 +0200 [thread overview]
Message-ID: <6ab9e591-f2f2-4267-8bdd-169ef0243e14@rivosinc.com> (raw)
In-Reply-To: <20240419-clinic-amusing-d23b1b6d2af2@spud>
On 19/04/2024 17:51, Conor Dooley wrote:
> On Thu, Apr 18, 2024 at 02:42:27PM +0200, Clément Léger wrote:
>> The Zc* standard extension for code reduction introduces new extensions.
>> This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp
>> are left out of this patch since they are targeting microcontrollers/
>> embedded CPUs instead of application processors.
>>
>> Signed-off-by: Clément Léger <cleger@rivosinc.com>
>> ---
>> arch/riscv/include/asm/hwcap.h | 4 ++++
>> arch/riscv/kernel/cpufeature.c | 4 ++++
>> 2 files changed, 8 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>> index 543e3ea2da0e..b7551bad341b 100644
>> --- a/arch/riscv/include/asm/hwcap.h
>> +++ b/arch/riscv/include/asm/hwcap.h
>> @@ -82,6 +82,10 @@
>> #define RISCV_ISA_EXT_ZACAS 73
>> #define RISCV_ISA_EXT_XANDESPMU 74
>> #define RISCV_ISA_EXT_ZIMOP 75
>> +#define RISCV_ISA_EXT_ZCA 76
>> +#define RISCV_ISA_EXT_ZCB 77
>> +#define RISCV_ISA_EXT_ZCD 78
>> +#define RISCV_ISA_EXT_ZCF 79
>>
>> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>>
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index 115ba001f1bc..09dee071274d 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
>> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
>> __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
>> + __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
>> + __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB),
>> + __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD),
>> + __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF),
>> __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
>> __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
>> __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
>
> Ye, this looks exactly like what I "feared".
Ok but for instance, Qemu actually set Zc* based on C/F/D. So the ISA
string containing theses dependencies should actually also be allowed.
So should we simply ignore them in the ISA string and always do our own
"post-processing" based on C/F/D ?
Thanks,
Clément
next prev parent reply other threads:[~2024-04-22 8:53 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 12:42 [PATCH v2 00/12] Add support for a few Zc* extensions as well as Zcmop Clément Léger
2024-04-18 12:42 ` [PATCH v2 01/12] dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description Clément Léger
2024-04-19 15:24 ` Conor Dooley
2024-04-18 12:42 ` [PATCH v2 02/12] riscv: dts: enable Zc* extensions when needed Clément Léger
2024-04-19 15:55 ` Conor Dooley
2024-04-18 12:42 ` [PATCH v2 03/12] dt-bindings: riscv: add Zc* extension rules implied by C extension Clément Léger
2024-04-19 15:49 ` Conor Dooley
2024-04-22 8:53 ` Clément Léger
2024-04-22 11:19 ` Conor Dooley
2024-04-22 11:40 ` Clément Léger
2024-04-18 12:42 ` [PATCH v2 04/12] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb Clément Léger
2024-04-19 15:51 ` Conor Dooley
2024-04-22 8:53 ` Clément Léger [this message]
2024-04-22 9:35 ` Conor Dooley
2024-04-22 11:14 ` Clément Léger
2024-04-22 11:36 ` Conor Dooley
2024-04-22 11:41 ` Clément Léger
2024-04-18 12:42 ` [PATCH v2 05/12] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions Clément Léger
2024-04-18 12:42 ` [PATCH v2 06/12] RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM Clément Léger
2024-04-18 13:20 ` Anup Patel
2024-04-18 12:42 ` [PATCH v2 07/12] KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test Clément Léger
2024-04-18 13:20 ` Anup Patel
2024-04-18 12:42 ` [PATCH v2 08/12] dt-bindings: riscv: add Zcmop ISA extension description Clément Léger
2024-04-19 15:50 ` Conor Dooley
2024-04-18 12:42 ` [PATCH v2 09/12] riscv: add ISA extension parsing for Zcmop Clément Léger
2024-04-18 12:42 ` [PATCH v2 10/12] riscv: hwprobe: export Zcmop ISA extension Clément Léger
2024-04-18 12:42 ` [PATCH v2 11/12] RISC-V: KVM: Allow Zcmop extension for Guest/VM Clément Léger
2024-04-18 13:21 ` Anup Patel
2024-04-18 12:42 ` [PATCH v2 12/12] KVM: riscv: selftests: Add Zcmop extension to get-reg-list test Clément Léger
2024-04-18 13:21 ` Anup Patel
2024-04-18 13:28 ` [PATCH v2 00/12] Add support for a few Zc* extensions as well as Zcmop Anup Patel
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