From: Charlie Jenkins <charlie@rivosinc.com>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: Deepak Gupta <debug@rivosinc.com>,
paul.walmsley@sifive.com, rick.p.edgecombe@intel.com,
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Subject: Re: [PATCH v3 05/29] riscv: zicfiss / zicfilp enumeration
Date: Wed, 8 May 2024 17:07:30 -0700 [thread overview]
Message-ID: <ZjwTwvaYSFAuB1qr@ghost> (raw)
In-Reply-To: <CABgGipX3vXeJ_RKnV17pE-NH6=L0XUF2sdKea7hZHbuq4skh_A@mail.gmail.com>
On Thu, May 09, 2024 at 08:00:00AM +0800, Andy Chiu wrote:
> Hi Deepak,
>
> On Thu, Apr 4, 2024 at 7:41 AM Deepak Gupta <debug@rivosinc.com> wrote:
> >
> > This patch adds support for detecting zicfiss and zicfilp. zicfiss and
> > zicfilp stands for unprivleged integer spec extension for shadow stack
> > and branch tracking on indirect branches, respectively.
> >
> > This patch looks for zicfiss and zicfilp in device tree and accordinlgy
> > lights up bit in cpu feature bitmap. Furthermore this patch adds detection
> > utility functions to return whether shadow stack or landing pads are
> > supported by cpu.
> >
> > Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> > ---
> > arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++
> > arch/riscv/include/asm/hwcap.h | 2 ++
> > arch/riscv/include/asm/processor.h | 1 +
> > arch/riscv/kernel/cpufeature.c | 2 ++
> > 4 files changed, 18 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index 0bd11862b760..f0fb8d8ae273 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -8,6 +8,7 @@
> >
> > #include <linux/bitmap.h>
> > #include <linux/jump_label.h>
> > +#include <linux/smp.h>
> > #include <asm/hwcap.h>
> > #include <asm/alternative-macros.h>
> > #include <asm/errno.h>
> > @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
> >
> > DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
> >
> > +static inline bool cpu_supports_shadow_stack(void)
> > +{
> > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
> > + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS));
> > +}
> > +
> > +static inline bool cpu_supports_indirect_br_lp_instr(void)
> > +{
> > + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) &&
> > + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP));
> > +}
> > +
> > #endif
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 1f2d2599c655..74b6c727f545 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,8 @@
> > #define RISCV_ISA_EXT_ZFA 71
> > #define RISCV_ISA_EXT_ZTSO 72
> > #define RISCV_ISA_EXT_ZACAS 73
> nit: two tabs for alignment
>
Deepak, I think you might be using tabs with a display size of 4 spaces
that causes a couple of places to have incorrect alignment but would
look correct with 4 spaces. Linux uses 8 spaces for tabs.
- Charlie
>
> > +#define RISCV_ISA_EXT_ZICFILP 74
> > +#define RISCV_ISA_EXT_ZICFISS 75
> >
> > #define RISCV_ISA_EXT_XLINUXENVCFG 127
> >
> > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> > index a8509cc31ab2..6c5b3d928b12 100644
> > --- a/arch/riscv/include/asm/processor.h
> > +++ b/arch/riscv/include/asm/processor.h
> > @@ -13,6 +13,7 @@
> > #include <vdso/processor.h>
> >
> > #include <asm/ptrace.h>
> > +#include <asm/hwcap.h>
> >
> > #ifdef CONFIG_64BIT
> > #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1))
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 79a5a35fab96..d052cad5b82f 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -263,6 +263,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> > __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts),
> > __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts),
> > + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts),
> > + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts),
> > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
> > __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
> > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
> > --
> > 2.43.2
> >
>
> Thanks,
> Andy
next prev parent reply other threads:[~2024-05-09 0:07 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-03 23:34 [PATCH v3 00/29] riscv control-flow integrity for usermode Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 01/29] riscv: envcfg save and restore on task switching Deepak Gupta
2024-05-09 0:10 ` Charlie Jenkins
2024-05-09 19:00 ` Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 02/29] riscv: define default value for envcfg for task Deepak Gupta
2024-05-10 22:33 ` Charlie Jenkins
2024-05-13 18:33 ` Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 03/29] riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv Deepak Gupta
2024-05-10 22:36 ` Charlie Jenkins
2024-04-03 23:34 ` [PATCH v3 04/29] riscv: zicfilp / zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2024-04-10 11:58 ` Rob Herring
2024-04-10 21:37 ` Deepak Gupta
2024-04-15 19:41 ` Rob Herring
2024-04-16 15:44 ` Deepak Gupta
2024-05-09 18:14 ` Conor Dooley
2024-05-09 18:46 ` Deepak Gupta
2024-05-09 20:32 ` Conor Dooley
2024-05-09 23:26 ` Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 05/29] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2024-05-09 0:00 ` Andy Chiu
2024-05-09 0:07 ` Charlie Jenkins [this message]
2024-04-03 23:34 ` [PATCH v3 06/29] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2024-05-10 22:37 ` Charlie Jenkins
2024-04-03 23:34 ` [PATCH v3 07/29] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2024-05-10 22:51 ` Charlie Jenkins
2024-04-03 23:34 ` [PATCH v3 08/29] mm: Define VM_SHADOW_STACK for RISC-V Deepak Gupta
2024-04-04 18:58 ` David Hildenbrand
2024-04-04 19:04 ` Mark Brown
2024-04-04 19:15 ` David Hildenbrand
2024-04-04 19:21 ` Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 09/29] mm: abstract shadow stack vma behind `vma_is_shadow_stack` Deepak Gupta
2024-04-04 19:02 ` David Hildenbrand
2024-04-04 21:39 ` Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 10/29] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2024-05-10 21:02 ` Charlie Jenkins
2024-05-13 17:47 ` Deepak Gupta
2024-05-13 18:36 ` Charlie Jenkins
2024-05-13 18:41 ` Deepak Gupta
2024-05-13 21:26 ` Charlie Jenkins
2024-05-12 16:24 ` Alexandre Ghiti
2024-05-13 18:29 ` Deepak Gupta
2024-04-03 23:34 ` [PATCH v3 11/29] riscv mm: manufacture shadow stack pte Deepak Gupta
2024-05-12 16:26 ` Alexandre Ghiti
2024-04-03 23:35 ` [PATCH v3 12/29] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2024-05-12 16:28 ` Alexandre Ghiti
2024-05-13 17:33 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 13/29] riscv mmu: write protect and shadow stack Deepak Gupta
2024-05-12 16:31 ` Alexandre Ghiti
2024-05-13 17:32 ` Deepak Gupta
2024-05-23 14:59 ` Alexandre Ghiti
2024-05-24 7:16 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 14/29] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2024-05-12 16:50 ` Alexandre Ghiti
2024-05-13 17:25 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 15/29] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2024-05-12 17:05 ` Alexandre Ghiti
2024-05-13 17:10 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 16/29] prctl: arch-agnostic prctl for shadow stack Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 17/29] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2024-05-10 23:29 ` Charlie Jenkins
2024-05-13 18:31 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 18/29] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 19/29] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 20/29] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2024-05-12 17:10 ` Alexandre Ghiti
2024-04-03 23:35 ` [PATCH v3 21/29] riscv/traps: Introduce software check exception Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 22/29] riscv sigcontext: adding cfi state field in sigcontext Deepak Gupta
2024-05-24 9:46 ` Andy Chiu
2024-05-24 19:11 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 23/29] riscv signal: Save and restore of shadow stack for signal Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 24/29] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 25/29] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 26/29] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 27/29] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2024-05-10 20:30 ` Charlie Jenkins
2024-05-13 17:07 ` Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 28/29] riscv: Documentation for shadow stack on riscv Deepak Gupta
2024-04-03 23:35 ` [PATCH v3 29/29] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2024-05-09 18:21 ` Charlie Jenkins
2024-05-09 19:16 ` Deepak Gupta
2024-05-10 1:20 ` Charlie Jenkins
2024-05-09 0:33 ` [PATCH v3 00/29] riscv control-flow integrity for usermode Charlie Jenkins
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