From: Sohil Mehta <sohil.mehta@intel.com>
To: "Luck, Tony" <tony.luck@intel.com>,
"x86@kernel.org" <x86@kernel.org>, Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H . Peter Anvin" <hpa@zytor.com>,
"Yazen Ghannam" <yazen.ghannam@amd.com>,
Arnd Bergmann <arnd@arndb.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Subject: Re: x86/mce: Is mce_is_memory_error() incorrect for Intel?
Date: Sat, 16 Dec 2023 04:41:36 +0530 [thread overview]
Message-ID: <314eedc5-c27e-4e63-b74a-7b06f64fdd86@intel.com> (raw)
In-Reply-To: <SJ1PR11MB60831E048B544C83E845D907FC8DA@SJ1PR11MB6083.namprd11.prod.outlook.com>
Thanks Tony for the explanation. It is very helpful.
>> Type Form
>> ---- ----
>> Generic Cache Hierarchy 000F 0000 0000 11LL
>> TLB Errors 000F 0000 0001 TTLL
>> Memory Controller Errors 000F 0000 1MMM CCCC
>> Cache Hierarchy Errors 000F 0001 RRRR TTLL
>> Extended Memory Errors 000F 0010 1MMM CCCC
>> Bus and Interconnect Errors 000F 1PPT RRRR IILL
>>
>> I am not sure what are the practical implications of getting
>> mce_is_memory_error() wrong. (This issue is completely theoretical right
>> now.) Any insights?
>
> This function is used to check whether an address is OS addressable memory
> (i.e. for a page that could be taken offline). That doesn't apply to the caching
> use case (the only way to "offline" such a page would be to offline each of the
> slow memory pages that it might be used for).
>
Makes sense. I am assuming these Extended Memory Errors will not be used
anymore (even for CXL.mem type configs) and we don't need to include
them in the mce_is_memory_error() check? I'll update the comment
accordingly.
> I'm not quite sure why bit 8 (cache hierarchy error) was added into this check,
> It would seem to have the same issues as extended memory.
>
From a little bit of digging it seems the check for "cache hierarchy
errors" was always there. Commit fa92c5869426 ("x86, mce: Support memory
error recovery for both UCNA and Deferred error in machine_check_poll")
introduced the original checks but maybe the intention at that time was
different? I see that the CEC stuff was added later so maybe the
original memory related failures were handled differently?
Now, should we remove the cache error related check from
mce_is_memory_error()?
prev parent reply other threads:[~2023-12-15 23:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-06 1:38 [PATCH] x86/mce: Update references to the Intel SDM Sohil Mehta
2023-12-06 10:13 ` Borislav Petkov
2023-12-06 23:03 ` Sohil Mehta
2023-12-13 19:27 ` x86/mce: Is mce_is_memory_error() incorrect for Intel? Sohil Mehta
2023-12-13 19:54 ` Luck, Tony
2023-12-15 23:11 ` Sohil Mehta [this message]
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