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AJvYcCXeXm/syPIQrQt2JshpnlQMDZIdkK8SEnm9X8nMpl0Dz/H2lBykKCUqRbSxcnJv2XDUKX63zRw3+qe9cBhcTalOIbWSRI7QWiPmnA== X-Gm-Message-State: AOJu0YzBIkcM387E4H1o9TzIFePAGqT0PCXFp/EoTnLQjxGBE+rbxIor PajZdPV0ePgeTloo84p0bvuxxOMXUZiYDpXjCFSPGfFesoIi4xa9kBKY7MjBEb0= X-Google-Smtp-Source: AGHT+IFMjfL7kc5atSQVs5RqNDVKOWw0871oLlfuW3vxv/8yUSCVntr1NwQgjxnL3bhXh2tYDPwLzw== X-Received: by 2002:a05:600c:a01:b0:41b:13a3:6183 with SMTP id z1-20020a05600c0a0100b0041b13a36183mr1736973wmp.24.1714728607700; Fri, 03 May 2024 02:30:07 -0700 (PDT) Received: from [10.1.1.109] ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id bi9-20020a05600c3d8900b00418db9e4228sm4988571wmb.29.2024.05.03.02.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 02:30:07 -0700 (PDT) Message-ID: <0106b6f58ce19752c2c685d128e5a480103ee91c.camel@linaro.org> Subject: Re: [PATCH v3 2/2] pinctrl: samsung: support a bus clock From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Krzysztof Kozlowski , Tudor Ambarus , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin Cc: Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 03 May 2024 10:30:06 +0100 In-Reply-To: References: <20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org> <20240426-samsung-pinctrl-busclock-v3-2-adb8664b8a7e@linaro.org> <9a960401-f41f-4902-bcbd-8f30f318ba98@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.3-1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Krzysztof, On Fri, 2024-05-03 at 11:13 +0200, Krzysztof Kozlowski wrote: > On 02/05/2024 12:41, Andr=C3=A9 Draszik wrote: > > I was initially thinking the same, but the clock seems to be required f= or > > register access only, interrupts are still being received and triggered > > with pclk turned off as per my testing. >=20 > Probably we could simplify this all and keep the clock enabled always, > when device is not suspended. Toggling clock on/off for every pin change > is also an overhead. Anyway, I merged the patches for now, because it > addresses real problem and seems like one of reasonable solutions. I had contemplated a global enable of the clock on driver instantiation as well, but in the end for me the reasons why I chose the fine-grained approach here instead were: * Since the clock is only needed for register access, it seems only natural to enable it during register accesses only. (The same would happen if we had support for automatic clock gating in Linux). * If we think about external GPIO interrupts, they are likely to occur very rarely (think button press by operator on some external keys or I2C interrupts), it seems a waste to have the clock running all the time. * drivers/i2c/busses/i2c-exynos5.c and drivers/soc/samsung/exynos-usi.c also kinda do it this way. Bus clocks are only enabled when needed (e.g. during transfer) (granted, the IPs (IP clocks) are also fully enabled/disabled in those drivers when idle, and there is no such thing here) Cheers, Andre'