From: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chester Lin <chester62515@gmail.com>,
Matthias Brugger <mbrugger@suse.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>,
Larisa Grigore <larisa.grigore@nxp.com>,
Lee Jones <lee@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Dong Aisheng <aisheng.dong@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>
Cc: Alberto Ruiz <aruizrui@redhat.com>,
Christophe Lizzi <clizzi@redhat.com>,
devicetree@vger.kernel.org, Enric Balletbo <eballetb@redhat.com>,
Eric Chanudet <echanude@redhat.com>,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
NXP S32 Linux Team <s32@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
"Vincent Guittot devicetree @ vger . kernel . org"
<vincent.guittot@linaro.org>
Subject: [PATCH v8 08/10] pinctrl: s32cc: implement GPIO functionality
Date: Tue, 20 Jan 2026 13:59:20 +0200 [thread overview]
Message-ID: <20260120115923.3463866-9-khristineandreea.barbulescu@oss.nxp.com> (raw)
In-Reply-To: <20260120115923.3463866-1-khristineandreea.barbulescu@oss.nxp.com>
From: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
Add basic GPIO functionality (request, free, get, set) for the existing
pinctrl SIUL2 driver since the hardware for pinctrl&GPIO is tightly
coupled.
Also, remove pinmux_ops which are no longer needed.
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com>
---
drivers/pinctrl/nxp/pinctrl-s32cc.c | 413 +++++++++++++++++++++++-----
1 file changed, 350 insertions(+), 63 deletions(-)
diff --git a/drivers/pinctrl/nxp/pinctrl-s32cc.c b/drivers/pinctrl/nxp/pinctrl-s32cc.c
index 50d5a01107eb..3e0c48068f08 100644
--- a/drivers/pinctrl/nxp/pinctrl-s32cc.c
+++ b/drivers/pinctrl/nxp/pinctrl-s32cc.c
@@ -40,6 +40,14 @@
#define S32_MSCR_ODE BIT(20)
#define S32_MSCR_OBE BIT(21)
+/* PGPDOs are 16bit registers that come in big endian
+ * order if they are grouped in pairs of two.
+ *
+ * For example, the order is PGPDO1, PGPDO0, PGPDO3, PGPDO2...
+ */
+#define S32_PGPD(N) (((N) ^ 1) * 2)
+#define S32_PGPD_SIZE 16
+
enum s32_write_type {
S32_PINCONF_UPDATE_ONLY,
S32_PINCONF_OVERWRITE,
@@ -97,6 +105,7 @@ struct s32_pinctrl_context {
* struct s32_pinctrl - private driver data
* @dev: a pointer back to containing device
* @pctl: a pointer to the pinctrl device structure
+ * @gc: a pointer to the gpio_chip
* @regions: reserved memory regions with start/end pin
* @info: structure containing information about the pin
* @gpio_configs: saved configurations for GPIO pins
@@ -108,6 +117,7 @@ struct s32_pinctrl_context {
struct s32_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
+ struct gpio_chip gc;
struct s32_pinctrl_mem_region *regions;
struct s32_pinctrl_soc_info *info;
struct list_head gpio_configs;
@@ -396,67 +406,6 @@ static int s32_pmx_get_groups(struct pinctrl_dev *pctldev,
return 0;
}
-static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int offset)
-{
- struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct gpio_pin_config *gpio_pin;
- unsigned int config;
- unsigned long flags;
- int ret;
-
- ret = s32_regmap_read(pctldev, offset, &config);
- if (ret)
- return ret;
-
- /* Save current configuration */
- gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL);
- if (!gpio_pin)
- return -ENOMEM;
-
- gpio_pin->pin_id = offset;
- gpio_pin->config = config;
- INIT_LIST_HEAD(&gpio_pin->list);
-
- spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);
- list_add(&gpio_pin->list, &ipctl->gpio_configs);
- spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags);
-
- /* GPIO pin means SSS = 0 */
- config &= ~S32_MSCR_SSS_MASK;
-
- return s32_regmap_write(pctldev, offset, config);
-}
-
-static void s32_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int offset)
-{
- struct s32_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct gpio_pin_config *gpio_pin, *tmp;
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);
-
- list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) {
- if (gpio_pin->pin_id == offset) {
- ret = s32_regmap_write(pctldev, gpio_pin->pin_id,
- gpio_pin->config);
- if (ret != 0)
- goto unlock;
-
- list_del(&gpio_pin->list);
- kfree(gpio_pin);
- break;
- }
- }
-
-unlock:
- spin_unlock_irqrestore(&ipctl->gpio_configs_lock, flags);
-}
-
static int s32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset,
@@ -480,8 +429,6 @@ static const struct pinmux_ops s32_pmx_ops = {
.get_function_name = s32_pmx_get_func_name,
.get_function_groups = s32_pmx_get_groups,
.set_mux = s32_pmx_set,
- .gpio_request_enable = s32_pmx_gpio_request_enable,
- .gpio_disable_free = s32_pmx_gpio_disable_free,
.gpio_set_direction = s32_pmx_gpio_set_direction,
};
@@ -700,6 +647,307 @@ static const struct pinconf_ops s32_pinconf_ops = {
.pin_config_group_dbg_show = s32_pinconf_group_dbg_show,
};
+static struct s32_pinctrl *to_s32_pinctrl(struct gpio_chip *chip)
+{
+ return container_of(chip, struct s32_pinctrl, gc);
+}
+
+static struct regmap *s32_gpio_get_pgpd_regmap(struct gpio_chip *chip,
+ unsigned int pin,
+ bool output)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(chip);
+ struct nxp_siul2_mfd *mfd;
+ u32 base, num;
+ int i;
+
+ mfd = dev_get_drvdata(ipctl->dev->parent);
+
+ for (i = 0; i < mfd->num_siul2; i++) {
+ base = mfd->siul2[i].gpio_base;
+ num = mfd->siul2[i].gpio_num;
+
+ if (pin >= base && pin < base + num)
+ return output ? mfd->siul2[i].regmaps[SIUL2_PGPDO] :
+ mfd->siul2[i].regmaps[SIUL2_PGPDI];
+ }
+
+ return NULL;
+}
+
+static int s32_gpio_request(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(gc);
+ struct pinctrl_dev *pctldev = ipctl->pctl;
+ struct gpio_pin_config *gpio_pin;
+ unsigned int config;
+ int ret;
+
+ ret = s32_regmap_read(pctldev, gpio, &config);
+ if (ret)
+ return ret;
+
+ /* Save current configuration */
+ gpio_pin = kmalloc(sizeof(*gpio_pin), GFP_KERNEL);
+ if (!gpio_pin)
+ return -ENOMEM;
+
+ gpio_pin->pin_id = gpio;
+ gpio_pin->config = config;
+
+ scoped_guard(spinlock_irqsave, &ipctl->gpio_configs_lock)
+ list_add(&gpio_pin->list, &ipctl->gpio_configs);
+
+ /* GPIO pin means SSS = 0 */
+ config &= ~S32_MSCR_SSS_MASK;
+
+ return s32_regmap_write(pctldev, gpio, config);
+}
+
+static void s32_gpio_free(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(gc);
+ struct pinctrl_dev *pctldev = ipctl->pctl;
+ struct gpio_pin_config *gpio_pin, *tmp;
+ int ret;
+
+ guard(spinlock_irqsave)(&ipctl->gpio_configs_lock);
+
+ list_for_each_entry_safe(gpio_pin, tmp, &ipctl->gpio_configs, list) {
+ if (gpio_pin->pin_id == gpio) {
+ ret = s32_regmap_write(pctldev, gpio_pin->pin_id,
+ gpio_pin->config);
+ if (ret != 0)
+ return;
+
+ list_del(&gpio_pin->list);
+ kfree(gpio_pin);
+ return;
+ }
+ }
+}
+
+static int s32_gpio_get_dir(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(chip);
+ unsigned int reg_value;
+ int ret;
+
+ ret = s32_regmap_read(ipctl->pctl, gpio, ®_value);
+ if (ret)
+ return ret;
+
+ if (!(reg_value & S32_MSCR_IBE))
+ return -EINVAL;
+
+ return reg_value & S32_MSCR_OBE ? GPIO_LINE_DIRECTION_OUT :
+ GPIO_LINE_DIRECTION_IN;
+}
+
+static unsigned int s32_pin2pad(unsigned int pin)
+{
+ return pin / S32_PGPD_SIZE;
+}
+
+static u16 s32_pin2mask(unsigned int pin)
+{
+ /**
+ * From Reference manual :
+ * PGPDOx[PPDOy] = GPDO(x × 16) + (15 - y)[PDO_(x × 16) + (15 - y)]
+ */
+ return BIT(S32_PGPD_SIZE - 1 - pin % S32_PGPD_SIZE);
+}
+
+static struct regmap *s32_gpio_get_regmap_offset_mask(struct gpio_chip *chip,
+ unsigned int gpio,
+ unsigned int *reg_offset,
+ u16 *mask,
+ bool output)
+{
+ struct regmap *regmap;
+ unsigned int pad;
+
+ regmap = s32_gpio_get_pgpd_regmap(chip, gpio, output);
+ if (!regmap)
+ return NULL;
+
+ *mask = s32_pin2mask(gpio);
+ pad = s32_pin2pad(gpio);
+
+ *reg_offset = S32_PGPD(pad);
+
+ return regmap;
+}
+
+static int s32_gpio_set_val(struct gpio_chip *chip, unsigned int gpio,
+ int value)
+{
+ unsigned int reg_offset;
+ struct regmap *regmap;
+ u16 mask;
+ int ret;
+
+ regmap = s32_gpio_get_regmap_offset_mask(chip, gpio, ®_offset,
+ &mask, true);
+ if (!regmap)
+ return -ENODEV;
+
+ value = value ? mask : 0;
+
+ ret = regmap_update_bits(regmap, reg_offset, mask, value);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int s32_gpio_set(struct gpio_chip *chip, unsigned int gpio,
+ int value)
+{
+ if (s32_gpio_get_dir(chip, gpio) != GPIO_LINE_DIRECTION_OUT)
+ return -EPERM;
+
+ return s32_gpio_set_val(chip, gpio, value);
+}
+
+static int s32_gpio_get(struct gpio_chip *chip, unsigned int gpio)
+{
+ unsigned int reg_offset, value;
+ struct regmap *regmap;
+ u16 mask;
+ int ret;
+
+ if (s32_gpio_get_dir(chip, gpio) != GPIO_LINE_DIRECTION_IN)
+ return -EINVAL;
+
+ regmap = s32_gpio_get_regmap_offset_mask(chip, gpio, ®_offset,
+ &mask, false);
+ if (!regmap)
+ return -EINVAL;
+
+ ret = regmap_read(regmap, reg_offset, &value);
+ if (ret)
+ return ret;
+
+ return !!(value & mask);
+}
+
+static int s32_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
+ int val)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(chip);
+
+ s32_gpio_set_val(chip, gpio, val);
+
+ return s32_pmx_gpio_set_direction(ipctl->pctl, NULL, gpio, false);
+}
+
+static int s32_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(chip);
+
+ return s32_pmx_gpio_set_direction(ipctl->pctl, NULL, gpio, true);
+}
+
+static bool s32_gpio_is_valid(struct gpio_chip *chip, unsigned int gpio)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(chip);
+ const struct s32_pinctrl_soc_data *soc_data;
+ const struct pinctrl_pin_desc *pins;
+ int i;
+
+ soc_data = ipctl->info->soc_data;
+ pins = ipctl->info->soc_data->pins;
+ for (i = 0; i < soc_data->npins && pins[i].number <= gpio; i++)
+ if (pins[i].number == gpio)
+ return true;
+
+ return false;
+}
+
+static int s32_init_valid_mask(struct gpio_chip *chip, unsigned long *mask,
+ unsigned int ngpios)
+{
+ struct s32_pinctrl *ipctl = to_s32_pinctrl(chip);
+ const struct s32_pinctrl_soc_data *soc_data;
+ const struct pinctrl_pin_desc *pins;
+ int i;
+
+ bitmap_zero(mask, ngpios);
+
+ soc_data = ipctl->info->soc_data;
+ pins = soc_data->pins;
+ for (i = 0; i < soc_data->npins && pins[i].number < ngpios; i++)
+ bitmap_set(mask, pins[i].number, 1);
+
+ return 0;
+}
+
+static int s32_gpio_gen_names(struct device *dev, struct gpio_chip *gc,
+ unsigned int cnt, char **names, char *ch_index,
+ unsigned int *num_index)
+{
+ unsigned int i;
+
+ for (i = 0; i < cnt; i++) {
+ if (i != 0 && !(*num_index % 16))
+ (*ch_index)++;
+
+ if (!s32_gpio_is_valid(gc, *num_index))
+ continue;
+
+ names[i] = devm_kasprintf(dev, GFP_KERNEL, "P%c_%02d",
+ *ch_index, 0xFU & (*num_index)++);
+ if (!names[i])
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int s32_gpio_populate_names(struct device *dev,
+ struct s32_pinctrl *ipctl)
+{
+ struct nxp_siul2_mfd *mfd = dev_get_drvdata(ipctl->dev->parent);
+ unsigned int num_index = 0;
+ char ch_index = 'A';
+ char **names;
+ int i, ret;
+
+ names = devm_kcalloc(dev, ipctl->gc.ngpio, sizeof(*names),
+ GFP_KERNEL);
+ if (!names)
+ return -ENOMEM;
+
+ for (i = 0; i < mfd->num_siul2; i++) {
+ /*
+ * Pin names' have the following naming: P${letter}_${index},
+ * where:
+ * - letters are from: {A, B, C, ...}
+ * - indexes from {0, 1, 2, ... 15}
+ *
+ * If the pin is a multiple of 16, its index needs to be 0.
+ */
+ if (mfd->siul2[i].gpio_base % 16 == 0)
+ num_index = 0;
+
+ ret = s32_gpio_gen_names(dev, &ipctl->gc,
+ mfd->siul2[i].gpio_num,
+ names + mfd->siul2[i].gpio_base,
+ &ch_index, &num_index);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Error setting SIUL2_%d names\n",
+ i);
+
+ ch_index++;
+ }
+
+ ipctl->gc.names = (const char *const *)names;
+
+ return 0;
+}
+
#ifdef CONFIG_PM_SLEEP
static bool s32_pinctrl_should_save(struct s32_pinctrl *ipctl,
unsigned int pin)
@@ -986,6 +1234,8 @@ int s32_pinctrl_probe(struct platform_device *pdev,
struct pinctrl_desc *s32_pinctrl_desc;
struct s32_pinctrl_soc_info *info;
struct s32_pinctrl *ipctl;
+ struct nxp_siul2_mfd *mfd;
+ struct gpio_chip *gc;
int ret;
if (!soc_data || !soc_data->pins || !soc_data->npins)
@@ -1068,5 +1318,42 @@ int s32_pinctrl_probe(struct platform_device *pdev,
dev_info(&pdev->dev, "Initialized S32 pinctrl driver\n");
+
+ /* Legacy bindings only cover pinctrl functionality. */
+ if (soc_data->legacy)
+ return 0;
+
+ mfd = dev_get_drvdata(pdev->dev.parent);
+ if (!mfd)
+ return dev_err_probe(&pdev->dev, -EINVAL, "Invalid parent!\n");
+
+ gc = &ipctl->gc;
+ gc->parent = &pdev->dev;
+ gc->label = dev_name(&pdev->dev);
+ gc->base = -1;
+ /* In some cases, there is a gap between the SIUL GPIOs. */
+ gc->ngpio = mfd->siul2[mfd->num_siul2 - 1].gpio_base +
+ mfd->siul2[mfd->num_siul2 - 1].gpio_num;
+ ret = s32_gpio_populate_names(&pdev->dev, ipctl);
+ if (ret)
+ return ret;
+
+ gc->set = s32_gpio_set;
+ gc->get = s32_gpio_get;
+ gc->set_config = gpiochip_generic_config;
+ gc->request = s32_gpio_request;
+ gc->free = s32_gpio_free;
+ gc->direction_output = s32_gpio_dir_out;
+ gc->direction_input = s32_gpio_dir_in;
+ gc->get_direction = s32_gpio_get_dir;
+ gc->init_valid_mask = s32_init_valid_mask;
+
+ ret = devm_gpiochip_add_data(&pdev->dev, gc, ipctl);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret,
+ "Unable to add gpiochip\n");
+
+ dev_info(&pdev->dev, "Initialized s32 GPIO functionality\n");
+
return 0;
}
--
2.50.1
next prev parent reply other threads:[~2026-01-20 11:59 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-20 11:59 [PATCH v8 00/10] gpio: siul2-s32g2: add initial GPIO driver Khristine Andreea Barbulescu
2026-01-20 11:59 ` [PATCH v8 01/10] dt-bindings: mfd: add support for the NXP SIUL2 module Khristine Andreea Barbulescu
2026-01-21 2:19 ` Rob Herring
2026-02-19 11:36 ` Khristine Andreea Barbulescu
2026-02-20 10:16 ` Krzysztof Kozlowski
2026-02-20 14:36 ` Khristine Andreea Barbulescu
2026-02-20 14:41 ` Krzysztof Kozlowski
2026-02-23 11:51 ` Khristine Andreea Barbulescu
2026-02-23 13:14 ` Krzysztof Kozlowski
2026-02-25 9:40 ` Ghennadi Procopciuc
2026-03-03 13:28 ` Ghennadi Procopciuc
2026-03-13 17:10 ` Krzysztof Kozlowski
2026-03-14 7:31 ` Arnd Bergmann
2026-03-23 7:57 ` Khristine Andreea Barbulescu
2026-03-23 8:07 ` Krzysztof Kozlowski
2026-03-31 7:48 ` Khristine Andreea Barbulescu
2026-03-31 10:11 ` Arnd Bergmann
2026-03-31 13:43 ` Khristine Andreea Barbulescu
2026-03-31 14:08 ` Arnd Bergmann
2026-03-23 15:33 ` Arnd Bergmann
2026-02-20 10:18 ` Krzysztof Kozlowski
2026-02-20 14:14 ` Khristine Andreea Barbulescu
2026-01-20 11:59 ` [PATCH v8 02/10] mfd: nxp-siul2: add support for NXP SIUL2 Khristine Andreea Barbulescu
2026-01-22 18:52 ` Sander Vanheule
2026-01-20 11:59 ` [PATCH v8 03/10] arm64: dts: s32g: change pinctrl node into the new mfd node Khristine Andreea Barbulescu
2026-01-27 9:13 ` Linus Walleij
2026-01-20 11:59 ` [PATCH v8 04/10] pinctrl: s32cc: use dev_err_probe() and improve error messages Khristine Andreea Barbulescu
2026-01-20 12:04 ` Bartosz Golaszewski
2026-01-20 11:59 ` [PATCH v8 05/10] pinctrl: s32cc: change to "devm_pinctrl_register_and_init" Khristine Andreea Barbulescu
2026-01-20 12:04 ` Bartosz Golaszewski
2026-01-20 11:59 ` [PATCH v8 06/10] pinctrl: s32g2: change the driver to also be probed as an MFD cell Khristine Andreea Barbulescu
2026-01-20 12:08 ` Bartosz Golaszewski
2026-01-23 13:57 ` Vincent Guittot
2026-01-20 11:59 ` [PATCH v8 07/10] pinctrl: s32cc: skip syscon child nodes when parsing funcs and groups Khristine Andreea Barbulescu
2026-01-20 12:16 ` Bartosz Golaszewski
2026-01-27 9:14 ` Linus Walleij
2026-01-20 11:59 ` Khristine Andreea Barbulescu [this message]
2026-01-23 13:56 ` [PATCH v8 08/10] pinctrl: s32cc: implement GPIO functionality Vincent Guittot
2026-01-20 11:59 ` [PATCH v8 09/10] MAINTAINERS: add MAINTAINER for NXP SIUL2 MFD driver Khristine Andreea Barbulescu
2026-01-27 9:17 ` Linus Walleij
2026-01-20 11:59 ` [PATCH v8 10/10] pinctrl: s32cc: set num_custom_params to 0 Khristine Andreea Barbulescu
2026-01-20 12:16 ` Bartosz Golaszewski
2026-01-20 13:45 ` Daniel Baluta
2026-01-20 19:49 ` [PATCH v8 00/10] gpio: siul2-s32g2: add initial GPIO driver Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260120115923.3463866-9-khristineandreea.barbulescu@oss.nxp.com \
--to=khristineandreea.barbulescu@oss.nxp.com \
--cc=aisheng.dong@nxp.com \
--cc=aruizrui@redhat.com \
--cc=brgl@bgdev.pl \
--cc=chester62515@gmail.com \
--cc=clizzi@redhat.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=eballetb@redhat.com \
--cc=echanude@redhat.com \
--cc=festevam@gmail.com \
--cc=ghennadi.procopciuc@nxp.com \
--cc=gregkh@linuxfoundation.org \
--cc=imx@lists.linux.dev \
--cc=kernel@pengutronix.de \
--cc=krzk+dt@kernel.org \
--cc=larisa.grigore@nxp.com \
--cc=lee@kernel.org \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mbrugger@suse.com \
--cc=ping.bai@nxp.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=s32@nxp.com \
--cc=shawnguo@kernel.org \
--cc=vincent.guittot@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).