From: Luca Weiss <luca.weiss@fairphone.com>
To: Bjorn Andersson <andersson@kernel.org>,
Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Luca Weiss <luca.weiss@fairphone.com>
Subject: [PATCH 1/5] dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl
Date: Wed, 28 Jan 2026 13:26:49 +0100 [thread overview]
Message-ID: <20260128-sm6350-lpi-tlmm-v1-1-36583f2a2a2a@fairphone.com> (raw)
In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com>
Add bindings for pin controller in Low Power Audio SubSystem (LPASS).
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml | 124 +++++++++++++++++++++
1 file changed, 124 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml
new file mode 100644
index 000000000000..2fa2484e7bc7
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 SoC LPASS LPI TLMM
+
+maintainers:
+ - Luca Weiss <luca.weiss@fairphone.com>
+
+description:
+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+ (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC.
+
+properties:
+ compatible:
+ const: qcom,sm6350-lpass-lpi-pinctrl
+
+ reg:
+ items:
+ - description: LPASS LPI TLMM Control and Status registers
+ - description: LPASS LPI MCC registers
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm6350-lpass-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm6350-lpass-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm6350-lpass-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-4])$"
+
+ function:
+ enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
+ dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
+ i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws,
+ swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
+ wsa_swr_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+allOf:
+ - $ref: qcom,lpass-lpi-common.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
+
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm6350-lpass-lpi-pinctrl";
+ reg = <0x033c0000 0x20000>,
+ <0x03550000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core",
+ "audio";
+
+ i2s1_active: i2s1-active-pins {
+ clk {
+ pins = "gpio6";
+ function = "i2s1_clk";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ ws {
+ pins = "gpio7";
+ function = "i2s1_ws";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ data {
+ pins = "gpio8", "gpio9";
+ function = "i2s1_data";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+ };
+ };
--
2.52.0
next prev parent reply other threads:[~2026-01-28 12:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 12:26 [PATCH 0/5] Add LPASS LPI pin controller support for SM6350 Luca Weiss
2026-01-28 12:26 ` Luca Weiss [this message]
2026-01-28 13:38 ` [PATCH 1/5] dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl Rob Herring (Arm)
2026-01-28 14:53 ` Luca Weiss
2026-01-28 12:26 ` [PATCH 2/5] pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control Luca Weiss
2026-01-28 12:35 ` Konrad Dybcio
2026-01-28 12:26 ` [PATCH 3/5] pinctrl: qcom: Add SM6350 LPASS LPI TLMM Luca Weiss
2026-01-28 12:39 ` Konrad Dybcio
2026-01-28 22:03 ` Dmitry Baryshkov
2026-01-28 12:26 ` [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller Luca Weiss
2026-01-28 22:16 ` Dmitry Baryshkov
2026-01-29 8:32 ` Luca Weiss
2026-01-29 11:19 ` Konrad Dybcio
2026-04-13 8:55 ` Luca Weiss
2026-04-22 13:08 ` Konrad Dybcio
2026-01-28 12:26 ` [PATCH 5/5] arm64: defconfig: Enable LPASS LPI pin controller for SM6350 Luca Weiss
2026-01-28 22:17 ` Dmitry Baryshkov
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