From: Luca Weiss <luca.weiss@fairphone.com>
To: Bjorn Andersson <andersson@kernel.org>,
Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Luca Weiss <luca.weiss@fairphone.com>
Subject: [PATCH 2/5] pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control
Date: Wed, 28 Jan 2026 13:26:50 +0100 [thread overview]
Message-ID: <20260128-sm6350-lpi-tlmm-v1-2-36583f2a2a2a@fairphone.com> (raw)
In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com>
On some platforms like SM6350 (Bitra), some pins have their slew
controlled with the SPARE_1 register - probably because they ran out of
register space for an extra pin. Add support for that.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 ++
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 20 ++++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 76aed3296279..15ced5027579 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -220,6 +220,8 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
+ else if (g->slew_base_spare_1)
+ reg = pctrl->slew_base + LPI_SPARE_1_REG;
else
reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index f48368492861..6ba0c4eba984 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -16,6 +16,7 @@ struct platform_device;
struct pinctrl_pin_desc;
#define LPI_SLEW_RATE_CTL_REG 0xa000
+#define LPI_SPARE_1_REG 0xc000
#define LPI_TLMM_REG_OFFSET 0x1000
#define LPI_SLEW_RATE_MAX 0x03
#define LPI_SLEW_BITS_SIZE 0x02
@@ -47,6 +48,7 @@ struct pinctrl_pin_desc;
{ \
.pin = id, \
.slew_offset = soff, \
+ .slew_base_spare_1 = false, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
@@ -62,6 +64,7 @@ struct pinctrl_pin_desc;
{ \
.pin = id, \
.slew_offset = soff, \
+ .slew_base_spare_1 = false, \
.funcs = (int[]){ \
LPI_MUX_gpio, \
LPI_MUX_##f1, \
@@ -73,6 +76,22 @@ struct pinctrl_pin_desc;
.pin_offset = poff, \
}
+#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \
+ { \
+ .pin = id, \
+ .slew_offset = soff, \
+ .slew_base_spare_1 = true, \
+ .funcs = (int[]){ \
+ LPI_MUX_gpio, \
+ LPI_MUX_##f1, \
+ LPI_MUX_##f2, \
+ LPI_MUX_##f3, \
+ LPI_MUX_##f4, \
+ }, \
+ .nfuncs = 5, \
+ .pin_offset = 0, \
+ }
+
/*
* Slew rate control is done in the same register as rest of the
* pin configuration.
@@ -87,6 +106,7 @@ struct lpi_pingroup {
unsigned int *funcs;
unsigned int nfuncs;
unsigned int pin_offset;
+ bool slew_base_spare_1;
};
struct lpi_function {
--
2.52.0
next prev parent reply other threads:[~2026-01-28 12:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 12:26 [PATCH 0/5] Add LPASS LPI pin controller support for SM6350 Luca Weiss
2026-01-28 12:26 ` [PATCH 1/5] dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl Luca Weiss
2026-01-28 13:38 ` Rob Herring (Arm)
2026-01-28 14:53 ` Luca Weiss
2026-01-28 12:26 ` Luca Weiss [this message]
2026-01-28 12:35 ` [PATCH 2/5] pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control Konrad Dybcio
2026-01-28 12:26 ` [PATCH 3/5] pinctrl: qcom: Add SM6350 LPASS LPI TLMM Luca Weiss
2026-01-28 12:39 ` Konrad Dybcio
2026-01-28 22:03 ` Dmitry Baryshkov
2026-01-28 12:26 ` [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller Luca Weiss
2026-01-28 22:16 ` Dmitry Baryshkov
2026-01-29 8:32 ` Luca Weiss
2026-01-29 11:19 ` Konrad Dybcio
2026-04-13 8:55 ` Luca Weiss
2026-04-22 13:08 ` Konrad Dybcio
2026-01-28 12:26 ` [PATCH 5/5] arm64: defconfig: Enable LPASS LPI pin controller for SM6350 Luca Weiss
2026-01-28 22:17 ` Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260128-sm6350-lpi-tlmm-v1-2-36583f2a2a2a@fairphone.com \
--to=luca.weiss@fairphone.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linusw@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=phone-devel@vger.kernel.org \
--cc=robh@kernel.org \
--cc=~postmarketos/upstreaming@lists.sr.ht \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).