From: "Sabau, Radu bogdan" <Radu.Sabau@analog.com>
To: "David Lechner" <dlechner@baylibre.com>,
"Lars-Peter Clausen" <lars@metafoo.de>,
"Hennerich, Michael" <Michael.Hennerich@analog.com>,
"Jonathan Cameron" <jic23@kernel.org>,
"Sa, Nuno" <Nuno.Sa@analog.com>,
"Andy Shevchenko" <andy@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Mark Brown" <broonie@kernel.org>,
"Linus Walleij" <linusw@kernel.org>,
"Bartosz Golaszewski" <brgl@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: "linux-iio@vger.kernel.org" <linux-iio@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>
Subject: RE: [PATCH v3 3/4] iio: adc: ad4691: add triggered buffer support
Date: Mon, 16 Mar 2026 15:56:40 +0000 [thread overview]
Message-ID: <LV9PR03MB84146ADC269645000849795AF740A@LV9PR03MB8414.namprd03.prod.outlook.com> (raw)
In-Reply-To: <7251a53a-100c-4867-ab4e-b7d2d019b26b@baylibre.com>
> -----Original Message-----
> From: David Lechner <dlechner@baylibre.com>
> Sent: Monday, March 16, 2026 5:38 PM
> To: Sabau, Radu bogdan <Radu.Sabau@analog.com>; Lars-Peter Clausen
> <lars@metafoo.de>; Hennerich, Michael <Michael.Hennerich@analog.com>;
> Jonathan Cameron <jic23@kernel.org>; Sa, Nuno <Nuno.Sa@analog.com>;
> Andy Shevchenko <andy@kernel.org>; Rob Herring <robh@kernel.org>;
> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Uwe Kleine-König <ukleinek@kernel.org>; Liam
> Girdwood <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Linus
> Walleij <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Philipp
> Zabel <p.zabel@pengutronix.de>
> Cc: linux-iio@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-pwm@vger.kernel.org; linux-
> gpio@vger.kernel.org
> Subject: Re: [PATCH v3 3/4] iio: adc: ad4691: add triggered buffer support
>
> [External]
>
> On 3/16/26 8:22 AM, Sabau, Radu bogdan wrote:
> >
> >
> >> -----Original Message-----
> >> From: David Lechner <dlechner@baylibre.com>
> >> Sent: Saturday, March 14, 2026 8:38 PM
> >
> > ...
> >
> >>> Both operating modes share a single IIO trigger and trigger handler.
> >>> The handler builds a complete scan — one u32 slot per channel at its
> >>> scan_index position, followed by a timestamp — and pushes it to the
> >>> IIO buffer in a single iio_push_to_buffers_with_ts() call.
> >>
> >> It would really help here to see some timing diagrams to know if we
> >> are implementing this right.
> >>
> >> For example, it isn't clear that in clocked mode if CNV triggers a
> >> single conversion in the sequencer (i.e. IIO_SAMP_FREQ should be
> >> info_mask_separate) or if it triggers the sequence (i.e. IIO_SAMP_FREQ
> >> should be info_mask_shared_by_all).
> >>
> >
> > The CNV triggers the sequence and IIO_SAMP_FREQ is
> info_mask_shared_by_all.
> >
> > As per datasheet page 31 (Accumulator Section), when each accumulator
> > receives a sample, the ACC_COUNT is increased. In clocked mode we
> > are setting the ACC_COUNT limit to 1, therefore having one sample per
> > channel (no oversampling as discussed in previous versions). So each
> > period of the CNV PWM is respective to one sample of a channel.
>
> Assuming that "a" channel means "one" channel...
>
> In this case then sampling_frequency should be per channel (separate).
>
> A sampling_frequency that is shared_by_all means that each period of
> CNV should trigger one sample each for _all_ channels. In other words,
> the sampling frequency gives one complete set of samples for all enabled
> channels pushed to the buffer.
>
Oh, ok then, will have them separate. I assumed that since the PWM period
is constant with each pulse, then the sampling rate will be the same for
each channel, thus having them as shared_by_all, but I assume you are
right about this in this case, I will have them as separate in this case, the
update will happen in the previous patch upon next version.
> >
> >>>
> >>> For CNV Clock Mode the GP0 pin is configured as DATA_READY output.
> The
> >>> IRQ handler stops conversions and fires the IIO trigger; the trigger
> >>> handler reads accumulated results from the AVG_IN registers via regmap
> >>> and restarts conversions for the next cycle.
> >>
> >> This seems OK, but I would kind of would expect that PWM as CNV to
> >> only be used for SPI offloading and not without SPI offloading.
> >>
> >> The ADC also has an internal oscillator, so it seems like it would
> >> be more useful to use that as a conversion trigger rather than
> >> requiring external hardware.
> >>
> >
> > This CNV is used in triggered buffer mode as well, not only in offload.
> > In this mode, CNV replaces the internal oscillator so CNV is the
> > conversion trigger (offload or not), which also introduces the advantage
> > of having a more flexible sampling rate.
>
> Yes, I understand that. We just never did that for any other chip yet.
> Usually, we would just use the internal oscillator on the chip instead
> for this sort of thing. But if you have applications engineers telling
> you that this is a setup they want to support, then we can do it.
I see, and yes, this is something that needs support. Appreciate the feedback!
>
> >>>
> >>> Manual mode channels use storagebits=32 (shift=8, realbits=16) so all
> >>> channel slots in the scan buffer are uniformly sized regardless of the
> >>> SPI wire format (24-bit transfer, 16-bit ADC data in bits[23:8]).
> >>
> >> I also don't understand why we are including the status bits in manual
> >> mode but not in CNV clock mode.
> >>
> >
> > In Manual Mode, status bits are received through SPI, because that's how
> > the hardware works. However, they are masked by the driver and thus not
> used.
>
> Usually there are registers to turn status on and off independently. If
> there isn't it could be helpful to add some comments in the code to
> remind us.
You are right, there is a register to turn this off, and they are actually disabled
by default, thus 16 storage bits can be used. Thanks for this!
next prev parent reply other threads:[~2026-03-16 15:57 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 10:07 [PATCH v3 0/4] iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family Radu Sabau via B4 Relay
2026-03-13 10:07 ` [PATCH v3 1/4] dt-bindings: iio: adc: add bindings for AD4691 family Radu Sabau via B4 Relay
2026-03-14 9:41 ` Krzysztof Kozlowski
2026-03-16 11:55 ` Sabau, Radu bogdan
2026-03-14 15:29 ` David Lechner
2026-03-14 16:19 ` David Lechner
2026-03-16 12:39 ` Sabau, Radu bogdan
2026-03-16 12:55 ` Sabau, Radu bogdan
2026-03-16 15:14 ` David Lechner
2026-03-16 15:47 ` Sabau, Radu bogdan
2026-03-14 18:18 ` David Lechner
2026-03-13 10:07 ` [PATCH v3 2/4] iio: adc: ad4691: add initial driver " Radu Sabau via B4 Relay
2026-03-13 10:58 ` Andy Shevchenko
2026-03-16 15:29 ` Sabau, Radu bogdan
2026-03-16 15:51 ` David Lechner
2026-03-16 15:57 ` Sabau, Radu bogdan
2026-03-16 16:13 ` Andy Shevchenko
2026-03-14 11:04 ` Nuno Sá
2026-03-16 14:29 ` Sabau, Radu bogdan
2026-03-16 16:00 ` Sabau, Radu bogdan
2026-03-14 16:36 ` David Lechner
2026-03-16 13:01 ` Sabau, Radu bogdan
2026-03-25 15:01 ` kernel test robot
2026-03-13 10:07 ` [PATCH v3 3/4] iio: adc: ad4691: add triggered buffer support Radu Sabau via B4 Relay
2026-03-13 11:13 ` Andy Shevchenko
2026-03-13 12:09 ` Sabau, Radu bogdan
2026-03-13 14:40 ` Andy Shevchenko
2026-03-14 18:37 ` David Lechner
2026-03-16 13:22 ` Sabau, Radu bogdan
2026-03-16 15:37 ` David Lechner
2026-03-16 15:56 ` Sabau, Radu bogdan [this message]
2026-03-16 16:44 ` David Lechner
2026-03-17 9:27 ` Sabau, Radu bogdan
2026-03-13 10:07 ` [PATCH v3 4/4] iio: adc: ad4691: add SPI offload support Radu Sabau via B4 Relay
2026-03-14 19:37 ` David Lechner
2026-03-16 13:31 ` Sabau, Radu bogdan
2026-03-13 11:14 ` [PATCH v3 0/4] iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family Andy Shevchenko
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