From: Daniel Golle <daniel@makrotopia.org>
To: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Daniel Golle" <daniel@makrotopia.org>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Chen-Yu Tsai" <wenst@chromium.org>,
"Weiyi Lu" <weiyi.lu@mediatek.com>,
"Chun-Jie Chen" <chun-jie.chen@mediatek.com>,
"Ikjoon Jang" <ikjn@chromium.org>,
"Sam Shih" <sam.shih@mediatek.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: [PATCH v2 1/3] clk: mediatek: add MUX_CLR_SET macro
Date: Thu, 26 Mar 2026 05:09:35 +0000 [thread overview]
Message-ID: <65e504ac2c2d19b4baba6b79a241788220b19b34.1774499536.git.daniel@makrotopia.org> (raw)
In-Reply-To: <cover.1774499536.git.daniel@makrotopia.org>
Some MediaTek SoCs (e.g. MT7988) define infra muxes that have neither
a clock gate nor an update register.
Add a MUX_CLR_SET convenience macro that takes only the mux register
offsets, bit shift, and width, hardcoding upd_ofs = 0 and
upd_shift = -1 so callers cannot accidentally pass bogus sentinel
values to wrongly-typed fields.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/clk/mediatek/clk-mux.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
index 151e56dcf8842..8a5d6aca43aa9 100644
--- a/drivers/clk/mediatek/clk-mux.h
+++ b/drivers/clk/mediatek/clk-mux.h
@@ -126,6 +126,11 @@ extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops;
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
mtk_mux_clr_set_upd_ops)
+#define MUX_CLR_SET(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width) \
+ MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
+ _mux_set_ofs, _mux_clr_ofs, _shift, _width, 0, -1)
+
#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \
--
2.53.0
next prev parent reply other threads:[~2026-03-26 5:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 5:09 [PATCH v2 0/3] clk: mediatek: fix gate-less mux definitions Daniel Golle
2026-03-26 5:09 ` Daniel Golle [this message]
2026-03-26 6:37 ` [PATCH v2 1/3] clk: mediatek: add MUX_CLR_SET macro Chen-Yu Tsai
2026-04-29 2:06 ` Stephen Boyd
2026-03-26 5:10 ` [PATCH v2 2/3] clk: mediatek: mt8192: use MUX_CLR_SET Daniel Golle
2026-03-26 6:37 ` Chen-Yu Tsai
2026-04-29 2:06 ` Stephen Boyd
2026-03-26 5:11 ` [PATCH v2 3/3] clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes Daniel Golle
2026-03-26 6:39 ` Chen-Yu Tsai
2026-04-29 2:06 ` Stephen Boyd
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