From: Daniel Golle <daniel@makrotopia.org>
To: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Daniel Golle" <daniel@makrotopia.org>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Chen-Yu Tsai" <wenst@chromium.org>,
"Weiyi Lu" <weiyi.lu@mediatek.com>,
"Chun-Jie Chen" <chun-jie.chen@mediatek.com>,
"Ikjoon Jang" <ikjn@chromium.org>,
"Sam Shih" <sam.shih@mediatek.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Subject: [PATCH v2 2/3] clk: mediatek: mt8192: use MUX_CLR_SET
Date: Thu, 26 Mar 2026 05:10:47 +0000 [thread overview]
Message-ID: <9667e8a7a0757f7fb9d6bb3fca105df97afd007b.1774499536.git.daniel@makrotopia.org> (raw)
In-Reply-To: <cover.1774499536.git.daniel@makrotopia.org>
The mfg_pll_sel mux has neither a clock gate nor an update register,
and upd_ofs is stored as u32, so the -1 truncates to 0xFFFFFFFF.
While upd_shift being -1 (as s8) prevents the update path from
executing at runtime, the bogus upd_ofs value is still stored in the
struct.
Use MUX_CLR_SET to avoid passing sentinel values to wrongly-typed
fields.
Fixes: 710573dee31b4 ("clk: mediatek: Add MT8192 basic clocks support")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/clk/mediatek/clk-mt8192.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 50b43807c60cf..6413619880483 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -579,8 +579,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
- MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
- mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
+ MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents,
+ 0x050, 0x054, 0x058, 18, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
/* CLK_CFG_5 */
--
2.53.0
next prev parent reply other threads:[~2026-03-26 5:10 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 5:09 [PATCH v2 0/3] clk: mediatek: fix gate-less mux definitions Daniel Golle
2026-03-26 5:09 ` [PATCH v2 1/3] clk: mediatek: add MUX_CLR_SET macro Daniel Golle
2026-03-26 6:37 ` Chen-Yu Tsai
2026-04-29 2:06 ` Stephen Boyd
2026-03-26 5:10 ` Daniel Golle [this message]
2026-03-26 6:37 ` [PATCH v2 2/3] clk: mediatek: mt8192: use MUX_CLR_SET Chen-Yu Tsai
2026-04-29 2:06 ` Stephen Boyd
2026-03-26 5:11 ` [PATCH v2 3/3] clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes Daniel Golle
2026-03-26 6:39 ` Chen-Yu Tsai
2026-04-29 2:06 ` Stephen Boyd
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