From: Biju Das <biju.das.jz@bp.renesas.com>
To: Hans Zhang <18255117159@163.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"kwilczynski@kernel.org" <kwilczynski@kernel.org>,
"mani@kernel.org" <mani@kernel.org>,
"vigneshr@ti.com" <vigneshr@ti.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"thomas.petazzoni@bootlin.com" <thomas.petazzoni@bootlin.com>,
"pali@kernel.org" <pali@kernel.org>,
"ryder.lee@mediatek.com" <ryder.lee@mediatek.com>,
"jianjun.wang@mediatek.com" <jianjun.wang@mediatek.com>,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
"mpillai@cadence.com" <mpillai@cadence.com>
Cc: "robh@kernel.org" <robh@kernel.org>,
"s-vadapalli@ti.com" <s-vadapalli@ti.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training
Date: Wed, 6 May 2026 15:31:28 +0000 [thread overview]
Message-ID: <TY3PR01MB11346620B7637A16120FDED26863F2@TY3PR01MB11346.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <20260506152346.166056-3-18255117159@163.com>
> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On Behalf Of Hans Zhang
> Sent: 06 May 2026 16:24
> Subject: [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link
> training
>
> The Cadence LGA (Legacy Architecture IP) PCIe host controller currently lacks the mandatory 100 ms
> delay after link training completes for speeds
> > 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1.
>
> Add a 'max_link_speed' field to struct cdns_pcie to record the maximum supported link speed (or the
> currently configured speed). In the common host layer function cdns_pcie_host_start_link(), after the
> link has been successfully established, call pcie_wait_after_link_train() to insert the required delay
> if max_link_speed > 2.
>
> Glue drivers must set max_link_speed appropriately (e.g., from the device tree property "max-link-
> speed") to enable the delay.
>
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
> drivers/pci/controller/cadence/pcie-cadence-host-common.c | 4 ++++
> drivers/pci/controller/cadence/pcie-cadence.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> index 2b0211870f02..51376f69d007 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c
> @@ -14,6 +14,7 @@
>
> #include "pcie-cadence.h"
> #include "pcie-cadence-host-common.h"
> +#include "../../pci.h"
>
> #define LINK_RETRAIN_TIMEOUT HZ
>
> @@ -115,6 +116,9 @@ int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc,
> if (!ret && rc->quirk_retrain_flag)
> ret = cdns_pcie_retrain(pcie, pcie_link_up);
>
> + if (!ret)
> + pcie_wait_after_link_train(pcie->max_link_speed);
> +
> return ret;
> }
> EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-
> cadence.h
> index 574e9cf4d003..e222b095d2b6 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -86,6 +86,7 @@ struct cdns_plat_pcie_of_data {
> * @ops: Platform-specific ops to control various inputs from Cadence PCIe
> * wrapper
> * @cdns_pcie_reg_offsets: Register bank offsets for different SoC
> + * @max_link_speed: maximum supported link speed
Maximum to make consistent with other comments?
> */
> struct cdns_pcie {
> void __iomem *reg_base;
> @@ -98,6 +99,7 @@ struct cdns_pcie {
> struct device_link **link;
> const struct cdns_pcie_ops *ops;
> const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
> + int max_link_speed;
unsigned int as speed cannot be negative??
Cheers,
Biju
> };
>
> /**
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-05-06 15:31 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-06 15:23 [PATCH v2 0/8] PCI: Add common helper for 100 ms delay after link training Hans Zhang
2026-05-06 15:23 ` [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:34 ` Biju Das
2026-05-06 16:16 ` Hans Zhang
2026-05-06 15:55 ` Manivannan Sadhasivam
2026-05-06 16:13 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Hans Zhang
2026-05-06 15:31 ` Biju Das [this message]
2026-05-06 16:21 ` Hans Zhang
2026-05-06 16:27 ` Biju Das
2026-05-06 16:31 ` Hans Zhang
2026-05-06 16:03 ` Manivannan Sadhasivam
2026-05-06 16:14 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 3/8] PCI: cadence: HPA: Add " Hans Zhang
2026-05-06 15:23 ` [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Hans Zhang
2026-05-06 16:04 ` Manivannan Sadhasivam
2026-05-06 16:11 ` Hans Zhang
2026-05-06 16:51 ` Manivannan Sadhasivam
2026-05-06 15:23 ` [PATCH v2 5/8] PCI: dwc: Use common pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:23 ` [PATCH v2 6/8] PCI: aardvark: Add 100 ms delay after link training Hans Zhang
2026-05-12 21:25 ` Pali Rohár
2026-05-13 7:00 ` Hans Zhang
2026-05-13 7:20 ` Pali Rohár
2026-05-13 7:34 ` Hans Zhang
2026-05-13 18:54 ` Pali Rohár
2026-05-15 15:04 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 7/8] PCI: mediatek-gen3: " Hans Zhang
2026-05-06 15:23 ` [PATCH v2 8/8] PCI: rzg3s-host: " Hans Zhang
2026-05-06 16:52 ` Claudiu Beznea
2026-05-09 16:25 ` Hans Zhang
2026-05-14 12:19 ` kernel test robot
2026-05-14 12:50 ` kernel test robot
2026-05-14 14:22 ` kernel test robot
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