From: Biju Das <biju.das.jz@bp.renesas.com>
To: Hans Zhang <18255117159@163.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"kwilczynski@kernel.org" <kwilczynski@kernel.org>,
"mani@kernel.org" <mani@kernel.org>,
"vigneshr@ti.com" <vigneshr@ti.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"thomas.petazzoni@bootlin.com" <thomas.petazzoni@bootlin.com>,
"pali@kernel.org" <pali@kernel.org>,
"ryder.lee@mediatek.com" <ryder.lee@mediatek.com>,
"jianjun.wang@mediatek.com" <jianjun.wang@mediatek.com>,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
"mpillai@cadence.com" <mpillai@cadence.com>
Cc: "robh@kernel.org" <robh@kernel.org>,
"s-vadapalli@ti.com" <s-vadapalli@ti.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper
Date: Wed, 6 May 2026 15:34:14 +0000 [thread overview]
Message-ID: <TY3PR01MB1134694C0F3D14E4A69EFB8CA863F2@TY3PR01MB11346.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <20260506152346.166056-2-18255117159@163.com>
> -----Original Message-----
> From: Hans Zhang <18255117159@163.com>
> Sent: 06 May 2026 16:24
> Subject: [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper
>
> PCIe r6.0, sec 6.6.1 (Conventional Reset) requires that for a Downstream Port supporting Link speeds
> greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before
> sending any Configuration Request.
>
> Introduce a static inline helper pcie_wait_after_link_train() that checks the given max_link_speed (2 =
> 5.0 GT/s, 3 = 8.0 GT/s, etc.) and calls
> msleep(100) only when the speed is greater than 5.0 GT/s. The helper uses the existing
> PCIE_RESET_CONFIG_WAIT_MS macro defined in pci.h.
>
> This allows multiple host controller drivers to share the same mandatory delay without duplicating the
> logic.
>
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
> drivers/pci/pci.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4a14f88e543a..a8705a2a2d85 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -60,6 +60,19 @@ struct pcie_tlp_log;
> */
> #define PCIE_RESET_CONFIG_WAIT_MS 100
>
> +/**
> + * pcie_wait_after_link_train - Wait 100 ms if link speed > 5 GT/s
> + * @max_link_speed: the maximum link speed (2 = 5.0 GT/s, 3 = 8.0 GT/s,
> +...)
> + *
> + * Must be called after Link training completes and before the first
> + * Configuration Request is sent.
> + */
> +static inline void pcie_wait_after_link_train(int max_link_speed) {
> + if (max_link_speed > 2)
> + msleep(PCIE_RESET_CONFIG_WAIT_MS);
> +}
Maybe move this patch to the user??
Cheers,
Biju
> +
> /* Parameters for the waiting for link up routine */
> #define PCIE_LINK_WAIT_MAX_RETRIES 10
> #define PCIE_LINK_WAIT_SLEEP_MS 90
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-05-06 15:34 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-06 15:23 [PATCH v2 0/8] PCI: Add common helper for 100 ms delay after link training Hans Zhang
2026-05-06 15:23 ` [PATCH v2 1/8] PCI: Add pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:34 ` Biju Das [this message]
2026-05-06 16:16 ` Hans Zhang
2026-05-06 15:55 ` Manivannan Sadhasivam
2026-05-06 16:13 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 2/8] PCI: cadence: LGA: Add max_link_speed field and 100 ms delay after link training Hans Zhang
2026-05-06 15:31 ` Biju Das
2026-05-06 16:21 ` Hans Zhang
2026-05-06 16:27 ` Biju Das
2026-05-06 16:31 ` Hans Zhang
2026-05-06 16:03 ` Manivannan Sadhasivam
2026-05-06 16:14 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 3/8] PCI: cadence: HPA: Add " Hans Zhang
2026-05-06 15:23 ` [PATCH v2 4/8] PCI: j721e: Set max_link_speed to enable 100 ms delay after link up Hans Zhang
2026-05-06 16:04 ` Manivannan Sadhasivam
2026-05-06 16:11 ` Hans Zhang
2026-05-06 16:51 ` Manivannan Sadhasivam
2026-05-06 15:23 ` [PATCH v2 5/8] PCI: dwc: Use common pcie_wait_after_link_train() helper Hans Zhang
2026-05-06 15:23 ` [PATCH v2 6/8] PCI: aardvark: Add 100 ms delay after link training Hans Zhang
2026-05-12 21:25 ` Pali Rohár
2026-05-13 7:00 ` Hans Zhang
2026-05-13 7:20 ` Pali Rohár
2026-05-13 7:34 ` Hans Zhang
2026-05-13 18:54 ` Pali Rohár
2026-05-15 15:04 ` Hans Zhang
2026-05-06 15:23 ` [PATCH v2 7/8] PCI: mediatek-gen3: " Hans Zhang
2026-05-06 15:23 ` [PATCH v2 8/8] PCI: rzg3s-host: " Hans Zhang
2026-05-06 16:52 ` Claudiu Beznea
2026-05-09 16:25 ` Hans Zhang
2026-05-14 12:19 ` kernel test robot
2026-05-14 12:50 ` kernel test robot
2026-05-14 14:22 ` kernel test robot
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