From: Icenowy Zheng <zhengxingda@iscas.ac.cn>
To: Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Huacai Chen <chenhuacai@kernel.org>,
WANG Xuerui <kernel@xen0n.name>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Icenowy Zheng <uwu@icenowy.me>, Yao Zi <me@ziyao.cc>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
loongarch@lists.linux.dev, linux-mips@vger.kernel.org,
Icenowy Zheng <zhengxingda@iscas.ac.cn>
Subject: [PATCH v4 3/6] dt-bindings: interrupt-controller: add LS7A PCH LPC
Date: Sat, 21 Mar 2026 17:20:29 +0800 [thread overview]
Message-ID: <20260321092032.3502701-4-zhengxingda@iscas.ac.cn> (raw)
In-Reply-To: <20260321092032.3502701-1-zhengxingda@iscas.ac.cn>
Loongson 7A series PCH contains an LPC controller with an interrupt
controller.
Add the device tree binding for the interrupt controller.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
---
.../loongson,pch-lpc.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
new file mode 100644
index 0000000000000..ff2a425b6f0b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-lpc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCH LPC Controller
+
+maintainers:
+ - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description:
+ This interrupt controller is found in the Loongson LS7A family of PCH for
+ accepting interrupts sent by LPC-connected peripherals and signalling PIC
+ via a single interrupt line when interrupts are available.
+
+properties:
+ compatible:
+ const: loongson,ls7a-lpc
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - interrupts
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ lpc: interrupt-controller@10002000 {
+ compatible = "loongson,ls7a-lpc";
+ reg = <0x10002000 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&pic>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.52.0
next prev parent reply other threads:[~2026-03-21 9:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-21 9:20 [PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 1/6] MIPS: loongson64: Override arch_dynirq_lower_bound to reserve LPC IRQs Icenowy Zheng
2026-03-26 21:40 ` Jiaxun Yang
2026-03-26 22:46 ` Thomas Bogendoerfer
2026-03-21 9:20 ` [PATCH v4 2/6] LoongArch: " Icenowy Zheng
2026-03-21 9:20 ` Icenowy Zheng [this message]
2026-03-21 11:45 ` [PATCH v4 3/6] dt-bindings: interrupt-controller: add LS7A PCH LPC Jiaxun Yang
2026-03-25 16:56 ` Rob Herring (Arm)
2026-03-21 9:20 ` [PATCH v4 4/6] irqchip/loongson-pch-lpc: Extract non-ACPI-related code from ACPI init Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 5/6] irqchip/loongson-pch-lpc: Add OF init code Icenowy Zheng
2026-03-21 9:20 ` [PATCH v4 6/6] irqchip/loongson-pch-lpc: Enable building on MIPS Loongson64 Icenowy Zheng
2026-03-21 11:46 ` Jiaxun Yang
2026-03-21 12:10 ` [PATCH v4 0/6] Add support for LS7A LPC IRQ for MIPS Loongson systems Huacai Chen
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