From: Shiji Yang <yangshiji66@outlook.com>
To: linux-mips@vger.kernel.org
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Shiji Yang <yangshiji66@outlook.com>
Subject: [PATCH 1/3] mips: pci-mt7620: fix bridge register access
Date: Wed, 18 Jun 2025 11:42:05 +0800 [thread overview]
Message-ID: <OSBPR01MB1670555F549B69B9A5E7F133BC72A@OSBPR01MB1670.jpnprd01.prod.outlook.com> (raw)
Host bridge registers and PCI RC control registers have different
memory base. pcie_m32() is used to write the RC control registers
instead of bridge registers. This patch introduces bridge_m32()
and use it to operate bridge registers to fix the access issue.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
arch/mips/pci/pci-mt7620.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
index 5c4bdf691..94b3c96a1 100644
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -87,6 +87,15 @@ static inline u32 bridge_r32(unsigned reg)
return ioread32(bridge_base + reg);
}
+static inline void bridge_m32(u32 clr, u32 set, unsigned reg)
+{
+ u32 val = bridge_r32(reg);
+
+ val &= ~clr;
+ val |= set;
+ bridge_w32(val, reg);
+}
+
static inline void pcie_w32(u32 val, unsigned reg)
{
iowrite32(val, pcie_base + reg);
@@ -228,7 +237,7 @@ static int mt7620_pci_hw_init(struct platform_device *pdev)
pcie_phy(0x68, 0xB4);
/* put core into reset */
- pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
+ bridge_m32(PCIRST, PCIRST, RALINK_PCI_PCICFG_ADDR);
reset_control_assert(rstpcie0);
/* disable power and all clocks */
@@ -318,7 +327,7 @@ static int mt7620_pci_probe(struct platform_device *pdev)
mdelay(50);
/* enable write access */
- pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
+ bridge_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
mdelay(100);
/* check if there is a card present */
@@ -340,7 +349,7 @@ static int mt7620_pci_probe(struct platform_device *pdev)
pcie_w32(0x06040001, RALINK_PCI0_CLASS);
/* enable interrupts */
- pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
+ bridge_m32(PCIINT2, PCIINT2, RALINK_PCI_PCIENA);
/* voodoo from the SDK driver */
pci_config_read(NULL, 0, 4, 4, &val);
--
2.39.5
next reply other threads:[~2025-06-18 3:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 3:42 Shiji Yang [this message]
2025-06-18 3:42 ` [PATCH 2/3] mips: pci-mt7620: add more register init values Shiji Yang
2026-04-06 12:29 ` Thomas Bogendoerfer
2025-06-18 3:42 ` [PATCH 3/3] mips: pci-mt7620: rework initialization procedure Shiji Yang
2026-04-06 12:29 ` Thomas Bogendoerfer
2026-02-24 1:14 ` [PATCH 1/3] mips: pci-mt7620: fix bridge register access Shiji Yang
2026-04-06 12:28 ` Thomas Bogendoerfer
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