From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>, "Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Haibo Xu" <haibo1.xu@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Björn Töpel" <bjorn@kernel.org>, "Marc Zyngier" <maz@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [RFC PATCH v3 12/17] irqchip: irq-sifive-plic: Add ACPI support
Date: Tue, 19 Dec 2023 23:15:21 +0530 [thread overview]
Message-ID: <20231219174526.2235150-13-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20231219174526.2235150-1-sunilvl@ventanamicro.com>
Add ACPI support in PLIC driver. In ACPI, IO devices use Global System
Interrupts (GSI) which is a flat space split across multiple PLICs.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Co-developed-by: Haibo Xu <haibo1.xu@intel.com>
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
---
arch/riscv/include/asm/irq.h | 6 +++
drivers/irqchip/irq-sifive-plic.c | 76 +++++++++++++++++++++++--------
2 files changed, 64 insertions(+), 18 deletions(-)
diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
index df59192a157d..7b14f3ebe242 100644
--- a/arch/riscv/include/asm/irq.h
+++ b/arch/riscv/include/asm/irq.h
@@ -28,6 +28,12 @@ struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi);
static inline struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) { return NULL; }
#endif
+#ifdef CONFIG_SIFIVE_PLIC
+struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi);
+#else
+static inline struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) { return NULL; }
+#endif
+
int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid);
int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid);
void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts);
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index c8f8a8cdcce1..d4c355ffa628 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -3,6 +3,7 @@
* Copyright (C) 2017 SiFive
* Copyright (C) 2018 Christoph Hellwig
*/
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -70,6 +71,8 @@ struct plic_priv {
unsigned long plic_quirks;
unsigned int nr_irqs;
unsigned long *prio_save;
+ u32 gsi_base;
+ int id;
};
struct plic_handler {
@@ -316,6 +319,10 @@ static int plic_irq_domain_translate(struct irq_domain *d,
{
struct plic_priv *priv = d->host_data;
+ /* For DT, gsi_base is always zero. */
+ if (fwspec->param[0] >= priv->gsi_base)
+ fwspec->param[0] = fwspec->param[0] - priv->gsi_base;
+
if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
return irq_domain_translate_twocell(d, fwspec, hwirq, type);
@@ -417,17 +424,31 @@ static const struct of_device_id plic_match[] = {
};
static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
- u32 *nr_irqs, u32 *nr_contexts)
+ u32 *nr_irqs, u32 *nr_contexts,
+ u32 *gsi_base, u32 *id)
{
struct device *dev = &pdev->dev;
+ struct acpi_madt_plic *plic;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(dev->fwnode))
- return -EINVAL;
+ if (!is_of_node(dev->fwnode)) {
+ plic = *(struct acpi_madt_plic **)dev_get_platdata(dev);
+ if (!plic) {
+ dev_err(dev, "PLIC platform data is NULL!\n");
+ return -EINVAL;
+ }
+
+ *nr_irqs = plic->num_irqs;
+ acpi_get_plic_nr_contexts(plic->id, nr_contexts);
+ if (WARN_ON(!*nr_contexts)) {
+ dev_err(dev, "no PLIC context available\n");
+ return -EINVAL;
+ }
+
+ *gsi_base = plic->gsi_base;
+ *id = plic->id;
+ return 0;
+ }
rc = of_property_read_u32(to_of_node(dev->fwnode),
"riscv,ndev", nr_irqs);
@@ -442,23 +463,28 @@ static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev,
return -EINVAL;
}
+ *gsi_base = 0;
+ *id = 0;
+
return 0;
}
static int plic_parse_context_parent_hwirq(struct platform_device *pdev,
- u32 context, u32 *parent_hwirq,
+ u32 context, u32 id, u32 *parent_hwirq,
unsigned long *parent_hartid)
{
struct device *dev = &pdev->dev;
struct of_phandle_args parent;
int rc;
- /*
- * Currently, only OF fwnode is supported so extend this
- * function for ACPI support.
- */
- if (!is_of_node(dev->fwnode))
- return -EINVAL;
+ if (!is_of_node(dev->fwnode)) {
+ rc = acpi_get_ext_intc_parent_hartid(id, context, parent_hartid);
+ if (rc)
+ return rc;
+
+ *parent_hwirq = RV_IRQ_EXT;
+ return 0;
+ }
rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent);
if (rc)
@@ -483,7 +509,9 @@ static int plic_probe(struct platform_device *pdev)
struct plic_priv *priv;
irq_hw_number_t hwirq;
struct resource *res;
+ int id, context_id;
bool cpuhp_setup;
+ u32 gsi_base;
if (is_of_node(dev->fwnode)) {
const struct of_device_id *id;
@@ -510,19 +538,21 @@ static int plic_probe(struct platform_device *pdev)
return -EIO;
}
- rc = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts);
+ rc = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &gsi_base, &id);
if (rc) {
dev_err(dev, "failed to parse irqs and contexts\n");
return rc;
}
priv->nr_irqs = nr_irqs;
+ priv->gsi_base = gsi_base;
+ priv->id = id;
priv->prio_save = devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL);
if (!priv->prio_save)
return -ENOMEM;
for (i = 0; i < nr_contexts; i++) {
- rc = plic_parse_context_parent_hwirq(pdev, i,
+ rc = plic_parse_context_parent_hwirq(pdev, i, priv->id,
&parent_hwirq, &hartid);
if (rc) {
dev_warn(dev, "hwirq for context%d not found\n", i);
@@ -574,13 +604,23 @@ static int plic_probe(struct platform_device *pdev)
goto done;
}
+ if (is_of_node(dev->fwnode)) {
+ context_id = i;
+ } else {
+ rc = acpi_get_plic_context(priv->id, i, &context_id);
+ if (rc) {
+ dev_warn(dev, "invalid context id for context%d\n", i);
+ continue;
+ }
+ }
+
cpumask_set_cpu(cpu, &priv->lmask);
handler->present = true;
handler->hart_base = priv->regs + CONTEXT_BASE +
- i * CONTEXT_SIZE;
+ context_id * CONTEXT_SIZE;
raw_spin_lock_init(&handler->enable_lock);
handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
- i * CONTEXT_ENABLE_SIZE;
+ context_id * CONTEXT_ENABLE_SIZE;
handler->priv = priv;
handler->enable_save = devm_kcalloc(dev,
--
2.39.2
next prev parent reply other threads:[~2023-12-19 17:46 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 17:45 [RFC PATCH v3 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 02/17] RISC-V: ACPI: Implement PCI related functionality Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 03/17] PCI: Make pci_create_root_bus() declare its reliance on MSI domains Sunil V L
2023-12-26 23:56 ` Bjorn Helgaas
2023-12-28 13:08 ` Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 04/17] ACPI: Add fw_devlink support for ACPI fwnode for IRQ dependency Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 05/17] ACPI: irq: Add support for deferred probe in acpi_register_gsi() Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 06/17] pnp.h: Reconfigure IRQ in pnp_irq() to support deferred probe Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 07/17] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 08/17] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 09/17] irqchip: riscv-intc: Add ACPI support for AIA Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 10/17] irqchip: riscv-imsic: Add ACPI support Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 11/17] irqchip: riscv-aplic: " Sunil V L
2023-12-19 17:45 ` Sunil V L [this message]
2023-12-19 17:45 ` [RFC PATCH v3 13/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 14/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 15/17] ACPI: RISC-V: Create APLIC platform device Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 16/17] ACPI: RISC-V: Create PLIC " Sunil V L
2023-12-19 17:45 ` [RFC PATCH v3 17/17] irqchip: riscv-intc: Set ACPI irqmodel Sunil V L
2023-12-19 17:50 ` [RFC PATCH v3 00/17] RISC-V: ACPI: Add external interrupt controller support Rafael J. Wysocki
2023-12-20 3:49 ` Sunil V L
2024-01-30 6:02 ` Sunil V L
2024-02-01 18:10 ` Rafael J. Wysocki
2024-02-02 12:17 ` Sunil V L
2024-03-04 10:20 ` Sunil V L
2024-04-15 15:09 ` Sunil V L
2024-04-15 15:18 ` Rafael J. Wysocki
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