From: Wei Huang <wei.huang2@amd.com>
To: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <netdev@vger.kernel.org>
Cc: <bhelgaas@google.com>, <corbet@lwn.net>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<alex.williamson@redhat.com>, <gospo@broadcom.com>,
<michael.chan@broadcom.com>, <ajit.khaparde@broadcom.com>,
<manoj.panicker2@amd.com>, <Eric.VanTassell@amd.com>,
<wei.huang2@amd.com>
Subject: [PATCH V1 4/9] PCI/TPH: Implement a command line option to force No ST Mode
Date: Thu, 9 May 2024 11:27:36 -0500 [thread overview]
Message-ID: <20240509162741.1937586-5-wei.huang2@amd.com> (raw)
In-Reply-To: <20240509162741.1937586-1-wei.huang2@amd.com>
When "No ST mode" is enabled, end-point devices can generate TPH headers
but with all steering tags treated as zero. A steering tag of zero is
interpreted as "using the default policy" by the root complex. This is
essential to quantify the benefit of steering tags for some given
workloads.
Co-developed-by: Eric Van Tassell <Eric.VanTassell@amd.com>
Signed-off-by: Eric Van Tassell <Eric.VanTassell@amd.com>
Reviewed-by: Andy Gospodarek <gospo@broadcom.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
---
.../admin-guide/kernel-parameters.txt | 1 +
drivers/pci/pci-driver.c | 7 ++++++-
drivers/pci/pci.c | 12 +++++++++++
drivers/pci/pcie/tph.c | 21 +++++++++++++++++++
include/linux/pci-tph.h | 3 +++
include/linux/pci.h | 1 +
6 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 5681600c6941..0adbbe291783 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4594,6 +4594,7 @@
norid [S390] ignore the RID field and force use of
one PCI domain per PCI function
notph [PCIE] Do not use PCIe TPH
+ nostmode [PCIE] Force TPH to use No ST Mode
pcie_aspm= [PCIE] Forcibly enable or ignore PCIe Active State Power
Management.
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index 9722d070c0ca..aa98843d9884 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -324,8 +324,13 @@ static long local_pci_probe(void *_ddi)
pci_dev->driver = pci_drv;
rc = pci_drv->probe(pci_dev, ddi->id);
if (!rc) {
- if (pci_tph_disabled())
+ if (pci_tph_disabled()) {
pcie_tph_disable(pci_dev);
+ return rc;
+ }
+
+ if (pci_tph_nostmode())
+ tph_set_dev_nostmode(pci_dev);
return rc;
}
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 06f9656f95bf..ba9ec6f1b51e 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -160,6 +160,9 @@ static bool pcie_ats_disabled;
/* If set, the PCIe TPH capability will not be used. */
static bool pcie_tph_disabled;
+/* If TPH is enabled, "No ST Mode" will be enforced. */
+static bool pcie_tph_nostmode;
+
/* If set, the PCI config space of each device is printed during boot. */
bool pci_early_dump;
@@ -175,6 +178,12 @@ bool pci_tph_disabled(void)
}
EXPORT_SYMBOL_GPL(pci_tph_disabled);
+bool pci_tph_nostmode(void)
+{
+ return pcie_tph_nostmode;
+}
+EXPORT_SYMBOL_GPL(pci_tph_nostmode);
+
/* Disable bridge_d3 for all PCIe ports */
static bool pci_bridge_d3_disable;
/* Force bridge_d3 for all PCIe ports */
@@ -6719,6 +6728,9 @@ static int __init pci_setup(char *str)
} else if (!strcmp(str, "notph")) {
pr_info("PCIe: TPH is disabled\n");
pcie_tph_disabled = true;
+ } else if (!strcmp(str, "nostmode")) {
+ pr_info("PCIe: TPH No ST Mode is enabled\n");
+ pcie_tph_nostmode = true;
} else if (!strncmp(str, "cbiosize=", 9)) {
pci_cardbus_io_size = memparse(str + 9, &str);
} else if (!strncmp(str, "cbmemsize=", 10)) {
diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c
index 5dc533b89a33..d5f7309fdf52 100644
--- a/drivers/pci/pcie/tph.c
+++ b/drivers/pci/pcie/tph.c
@@ -43,6 +43,27 @@ static int tph_set_reg_field_u32(struct pci_dev *dev, u8 offset, u32 mask,
return ret;
}
+int tph_set_dev_nostmode(struct pci_dev *dev)
+{
+ int ret;
+
+ /* set ST Mode Select to "No ST Mode" */
+ ret = tph_set_reg_field_u32(dev, PCI_TPH_CTRL,
+ PCI_TPH_CTRL_MODE_SEL_MASK,
+ PCI_TPH_CTRL_MODE_SEL_SHIFT,
+ PCI_TPH_NO_ST_MODE);
+ if (ret)
+ return ret;
+
+ /* set "TPH Requester Enable" to "TPH only" */
+ ret = tph_set_reg_field_u32(dev, PCI_TPH_CTRL,
+ PCI_TPH_CTRL_REQ_EN_MASK,
+ PCI_TPH_CTRL_REQ_EN_SHIFT,
+ PCI_TPH_REQ_TPH_ONLY);
+
+ return ret;
+}
+
int pcie_tph_disable(struct pci_dev *dev)
{
return tph_set_reg_field_u32(dev, PCI_TPH_CTRL,
diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h
index e187d7e89e8c..95269afc8b7d 100644
--- a/include/linux/pci-tph.h
+++ b/include/linux/pci-tph.h
@@ -11,9 +11,12 @@
#ifdef CONFIG_PCIE_TPH
int pcie_tph_disable(struct pci_dev *dev);
+int tph_set_dev_nostmode(struct pci_dev *dev);
#else
static inline int pcie_tph_disable(struct pci_dev *dev)
{ return -EOPNOTSUPP; }
+static inline int tph_set_dev_nostmode(struct pci_dev *dev)
+{ return -EOPNOTSUPP; }
#endif
#endif /* LINUX_PCI_TPH_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 63aa6f888c90..6781a1bd28c5 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1867,6 +1867,7 @@ static inline bool pci_aer_available(void) { return false; }
bool pci_ats_disabled(void);
bool pci_tph_disabled(void);
+bool pci_tph_nostmode(void);
#ifdef CONFIG_PCIE_PTM
int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
--
2.44.0
next prev parent reply other threads:[~2024-05-09 16:28 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 16:27 [PATCH V1 0/9] PCIe TPH and cache direct injection support Wei Huang
2024-05-09 16:27 ` [PATCH V1 1/9] PCI: Introduce PCIe TPH support framework Wei Huang
2024-05-09 16:27 ` [PATCH V1 2/9] PCI: Add TPH related register definition Wei Huang
2024-05-09 16:27 ` [PATCH V1 3/9] PCI/TPH: Implement a command line option to disable TPH Wei Huang
2024-05-09 16:27 ` Wei Huang [this message]
2024-05-09 16:27 ` [PATCH V1 5/9] PCI/TPH: Introduce API functions to get/set steering tags Wei Huang
2024-05-10 3:07 ` kernel test robot
2024-05-11 20:15 ` Simon Horman
2024-05-13 13:29 ` Wei Huang
2024-05-09 16:27 ` [PATCH V1 6/9] PCI/TPH: Retrieve steering tag from ACPI _DSM Wei Huang
2024-05-10 4:20 ` kernel test robot
2024-05-10 5:24 ` kernel test robot
2024-05-09 16:27 ` [PATCH V1 7/9] PCI/TPH: Add TPH documentation Wei Huang
2024-05-15 12:11 ` Bagas Sanjaya
2024-05-09 16:27 ` [PATCH V1 8/9] bnxt_en: Add TPH support in BNXT driver Wei Huang
2024-05-09 21:50 ` Vadim Fedorenko
2024-05-10 3:55 ` Ajit Khaparde
2024-05-10 10:35 ` Vadim Fedorenko
2024-05-10 15:23 ` Andy Gospodarek
2024-05-10 20:03 ` David Wei
2024-05-10 20:33 ` Andy Gospodarek
2024-05-10 20:33 ` Vadim Fedorenko
2024-05-10 20:37 ` Andy Gospodarek
2024-05-10 3:10 ` Somnath Kotur
2024-05-09 16:27 ` [PATCH V1 9/9] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang
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