From: Randolph Lin <randolph@andestech.com>
To: <linux-kernel@vger.kernel.org>
Cc: <linux-pci@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<devicetree@vger.kernel.org>, <jingoohan1@gmail.com>,
<mani@kernel.org>, <lpieralisi@kernel.org>,
<kwilczynski@kernel.org>, <robh@kernel.org>,
<bhelgaas@google.com>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <alex@ghiti.fr>, <aou@eecs.berkeley.edu>,
<palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
<ben717@andestech.com>, <inochiama@gmail.com>,
<thippeswamy.havalige@amd.com>, <namcao@linutronix.de>,
<shradha.t@samsung.com>, <pjw@kernel.org>,
<randolph.sklin@gmail.com>, <tim609@andestech.com>,
Randolph Lin <randolph@andestech.com>
Subject: [PATCH v9 1/4] dt-bindings: PCI: Add Andes QiLai PCIe support
Date: Thu, 23 Oct 2025 20:09:30 +0800 [thread overview]
Message-ID: <20251023120933.2427946-2-randolph@andestech.com> (raw)
In-Reply-To: <20251023120933.2427946-1-randolph@andestech.com>
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Only one example is required in the DTS bindings YAML file.
Signed-off-by: Randolph Lin <randolph@andestech.com>
---
.../bindings/pci/andestech,qilai-pcie.yaml | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
new file mode 100644
index 000000000000..7eca3be2c8f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andes QiLai PCIe host controller
+
+description:
+ Andes QiLai PCIe host controller is based on the Synopsys DesignWare
+ PCI core.
+
+maintainers:
+ - Randolph Lin <randolph@andestech.com>
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ const: andestech,qilai-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: APB registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: apb
+ - const: config
+
+ ranges:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: msi
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@80000000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x0 0x80000000 0x0 0x20000000>,
+ <0x0 0x04000000 0x0 0x00001000>,
+ <0x0 0x00000000 0x0 0x00010000>;
+ reg-names = "dbi", "apb", "config";
+
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x0000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
--
2.34.1
next prev parent reply other threads:[~2025-10-23 12:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-23 12:09 [PATCH v9 0/4] Add support for Andes Qilai SoC PCIe controller Randolph Lin
2025-10-23 12:09 ` Randolph Lin [this message]
2025-10-27 13:38 ` [PATCH v9 1/4] dt-bindings: PCI: Add Andes QiLai PCIe support Rob Herring (Arm)
2025-10-23 12:09 ` [PATCH v9 2/4] riscv: dts: andes: Add PCIe node into the QiLai SoC Randolph Lin
2025-10-23 12:09 ` [PATCH v9 3/4] PCI: andes: Add Andes QiLai SoC PCIe host driver support Randolph Lin
2025-10-23 12:09 ` [PATCH v9 4/4] MAINTAINERS: Add maintainers for Andes QiLai PCIe driver Randolph Lin
2025-10-23 20:45 ` [PATCH v9 0/4] Add support for Andes Qilai SoC PCIe controller Bjorn Helgaas
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