From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Lukas Wunner <lukas@wunner.de>
Subject: Re: [PATCH v3] PCI/PTM: Do not enable PTM solely based on the capability existense
Date: Tue, 11 Nov 2025 07:01:28 +0100 [thread overview]
Message-ID: <20251111060128.GU2912318@black.igk.intel.com> (raw)
In-Reply-To: <20251111001023.GA2143615@bhelgaas>
On Mon, Nov 10, 2025 at 06:10:23PM -0600, Bjorn Helgaas wrote:
> On Fri, Oct 31, 2025 at 07:09:59AM +0100, Mika Westerberg wrote:
> > On Thu, Oct 30, 2025 at 03:59:37PM -0500, Bjorn Helgaas wrote:
> > > On Thu, Oct 30, 2025 at 02:46:05PM +0100, Mika Westerberg wrote:
> > > > It is not advisable to enable PTM solely based on the fact that the
> > > > capability exists. Instead there are separate bits in the capability
> > > > register that need to be set for the feature to be enabled for a given
> > > > component (this is suggestion from Intel PCIe folks, and also shown in
> > > > PCIe r7.0 sec 6.21.1 figure 6-21):
> > >
> > > Can we start with a minimal statement of what's wrong? Is the problem
> > > that 01:00.0 sent a PTM Request Message that 00:07.0 detected as an
> > > ACS violation?
> >
> > The problem is that once the PCIe Switch is hotplugged we get tons of AER
> > errors like below (here upstream port is 2b:00.0, in the previous example
> > it was 01:00.0):
> >
> > [ 156.337979] pci 0000:2b:00.0: PTM enabled, 4ns granularity
> > [ 156.350822] pcieport 0000:00:07.1: AER: Multiple Uncorrectable (Non-Fatal) error message received from 0000:00:07.1
> > [ 156.361417] pcieport 0000:00:07.1: PCIe Bus Error: severity=Uncorrectable (Non-Fatal), type=Transaction Layer, (Receiver ID)
> > [ 156.372656] pcieport 0000:00:07.1: device [8086:e44f] error status/mask=00200000/00000000
> > [ 156.381041] pcieport 0000:00:07.1: [21] ACSViol (First)
> > [ 156.387842] pcieport 0000:00:07.1: AER: TLP Header: 0x34000000 0x00000052 0x00000000 0x00000000
>
> If I read this right:
>
> 0x34000000 is 0011 0100 0...0
> Fmt 001 4 DW header, no data (PCIe r7.0, sec 2.2.1.1)
> Type 10100 Message Request, Local - Terminate at Receiver (2.2.1.1, 2.2.8)
>
> 0x00000052 is 0...0 0101 0010
> 0x0000 Requester ID
> 0101 0010 PTM Request (2.2.8.10)
>
> The fact that the Request ID is 0x0000 and the error is an ACS
> Violation looks like the implementation note in sec 6.12.1.1:
>
> Functions are permitted to transmit Upstream Messages before they
> have been assigned a Bus Number. Such messages will have a Requester
> ID with a Bus Number of 00h. If the Downstream Port has ACS Source
> Validation enabled, these Messages (see Table F-1, Section 2.2.8.2,
> and Section 6.22.1) will likely be detected as an ACS Violation
> error.
Okay thanks for looking.
> So I assume 2b:00.0 sent a PTM Request with Requester ID of 0, and
> 00:07.1 logged the ACS violation. It's odd that 2b:00.0 would send a
> PTM request if it doesn't advertise the PTM Requester role. Also odd
> that it doesn't seem to know its Bus Number. It's supposed to capture
> that from every config write request (sec 2.2.9.1), and I would think
> it should have seen several by now including the one that enable PTM.
Indeed but for some reason the flood of AER ACS violations start
immediately after we enabled it. Even if it has the bus number already
assigned.
> But I think your fix is right even if we don't understand exactly how
> we got there. Are you planning an update, or ...? Just wanted to
> make sure we're not waiting for each other.
Yes, I have the new version ready. Tested it yesterday and was planning to
send it out today.
prev parent reply other threads:[~2025-11-11 6:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-30 13:46 [PATCH v3] PCI/PTM: Do not enable PTM solely based on the capability existense Mika Westerberg
2025-10-30 20:59 ` Bjorn Helgaas
2025-10-31 6:09 ` Mika Westerberg
2025-11-11 0:10 ` Bjorn Helgaas
2025-11-11 6:01 ` Mika Westerberg [this message]
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