From: Hans Zhang <18255117159@163.com>
To: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, hans.zhang@cixtech.com
Cc: robh@kernel.org, mpillai@cadence.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>
Subject: [PATCH v4 1/2] PCI: cadence: Add HPA architecture flag
Date: Fri, 8 May 2026 11:41:00 +0800 [thread overview]
Message-ID: <20260508034101.1910036-2-18255117159@163.com> (raw)
In-Reply-To: <20260508034101.1910036-1-18255117159@163.com>
Add a boolean flag 'is_hpa' to the cdns_pcie structure to indicate
that the controller is part of a Heterogeneous Processor Architecture
(HPA) system. This flag will be used by subsequent patches to handle
HPA-specific register layouts and behaviors.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/cadence/pci-sky1.c | 1 +
drivers/pci/controller/cadence/pcie-cadence.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/controller/cadence/pci-sky1.c
index cd55c64e58a9..e1f4a98e2ab6 100644
--- a/drivers/pci/controller/cadence/pci-sky1.c
+++ b/drivers/pci/controller/cadence/pci-sky1.c
@@ -174,6 +174,7 @@ static int sky1_pcie_probe(struct platform_device *pdev)
cdns_pcie->reg_base = pcie->reg_base;
cdns_pcie->msg_res = pcie->msg_res;
cdns_pcie->is_rc = true;
+ cdns_pcie->is_hpa = true;
reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
if (!reg_off) {
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 574e9cf4d003..9a464cbaf073 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -80,6 +80,7 @@ struct cdns_plat_pcie_of_data {
* @msg_res: Region for send message to map PCI accesses
* @dev: PCIe controller
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
+ * @is_hpa: indicates if the architecture is HPA
* @phy_count: number of supported PHY devices
* @phy: list of pointers to specific PHY control blocks
* @link: list of pointers to corresponding device link representations
@@ -93,6 +94,7 @@ struct cdns_pcie {
struct resource *msg_res;
struct device *dev;
bool is_rc;
+ bool is_hpa;
int phy_count;
struct phy **phy;
struct device_link **link;
--
2.34.1
next prev parent reply other threads:[~2026-05-08 3:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 3:40 [PATCH v4 0/2] PCI: cadence: Add LTSSM debugfs Hans Zhang
2026-05-08 3:41 ` Hans Zhang [this message]
2026-05-08 3:41 ` [PATCH v4 2/2] PCI: cadence: Add debugfs property to provide LTSSM status of the PCIe link Hans Zhang
2026-05-08 4:19 ` sashiko-bot
2026-05-08 4:31 ` Hans Zhang
2026-05-13 5:23 ` Aksh Garg
2026-05-13 6:11 ` Manikandan Karunakaran Pillai
2026-05-13 6:39 ` Hans Zhang
2026-05-13 7:08 ` Manikandan Karunakaran Pillai
2026-05-13 8:34 ` Aksh Garg
2026-05-13 8:55 ` Hans Zhang
2026-05-13 11:30 ` Aksh Garg
2026-05-13 12:04 ` Hans Zhang
2026-05-14 1:39 ` Manikandan Karunakaran Pillai
2026-05-14 1:46 ` Hans Zhang
2026-05-14 4:25 ` Manikandan Karunakaran Pillai
2026-05-13 6:37 ` Hans Zhang
2026-05-13 8:25 ` Aksh Garg
2026-05-13 8:29 ` Hans Zhang
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