From: Hans Zhang <18255117159@163.com>
To: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, s-vadapalli@ti.com,
a-garg7@ti.com
Cc: robh@kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>
Subject: [PATCH v2 1/3] PCI: cadence: Fix Root Port configuration space access for LGA IP
Date: Sat, 9 May 2026 21:07:14 +0800 [thread overview]
Message-ID: <20260509130716.2104103-2-18255117159@163.com> (raw)
In-Reply-To: <20260509130716.2104103-1-18255117159@163.com>
On LGA (Legacy) Cadence IP, the Root Port configuration space is
located at offset CDNS_PCIE_RP_BASE (0x00200000) from the controller's
base address. However, the standard accessors cdns_pcie_read_cfg_*()
did not include this offset when operating in RC mode, causing any
configuration read (including capability list walking) to access the
wrong register region (Local Management space).
Additionally, cdns_pcie_read_cfg_dword() used a direct readl()
instead of the more general cdns_pcie_read_sz(), breaking symmetry
with byte/word accesses.
Fix this by:
Adding CDNS_PCIE_RP_BASE to the address for RC mode on non-HPA
(i.e. LGA) IP.
Replacing cdns_pcie_readl() with cdns_pcie_read_sz() in the dword
accessor for consistency.
This change enables correct capability discovery for Root Ports on LGA
platforms.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/cadence/pcie-cadence.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index a1c531fd2061..c057f4b393e6 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -433,6 +433,9 @@ static inline int cdns_pcie_read_cfg_byte(struct cdns_pcie *pcie, int where,
{
void __iomem *addr = pcie->reg_base + where;
+ if ((pcie->is_rc) && (!pcie->is_hpa))
+ addr += CDNS_PCIE_RP_BASE;
+
*val = cdns_pcie_read_sz(addr, 0x1);
return PCIBIOS_SUCCESSFUL;
}
@@ -442,6 +445,9 @@ static inline int cdns_pcie_read_cfg_word(struct cdns_pcie *pcie, int where,
{
void __iomem *addr = pcie->reg_base + where;
+ if ((pcie->is_rc) && (!pcie->is_hpa))
+ addr += CDNS_PCIE_RP_BASE;
+
*val = cdns_pcie_read_sz(addr, 0x2);
return PCIBIOS_SUCCESSFUL;
}
@@ -449,7 +455,12 @@ static inline int cdns_pcie_read_cfg_word(struct cdns_pcie *pcie, int where,
static inline int cdns_pcie_read_cfg_dword(struct cdns_pcie *pcie, int where,
u32 *val)
{
- *val = cdns_pcie_readl(pcie, where);
+ void __iomem *addr = pcie->reg_base + where;
+
+ if ((pcie->is_rc) && (!pcie->is_hpa))
+ addr += CDNS_PCIE_RP_BASE;
+
+ *val = cdns_pcie_read_sz(addr, 0x4);
return PCIBIOS_SUCCESSFUL;
}
--
2.34.1
next prev parent reply other threads:[~2026-05-09 13:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-09 13:07 [PATCH v2 0/3] PCI: cadence: Fix and generalize PCIe capability offset for Root Port Hans Zhang
2026-05-09 13:07 ` Hans Zhang [this message]
2026-05-09 13:07 ` [PATCH v2 2/3] PCI: cadence: Add cdns_pcie_get_pcie_cap() helper and cache capability offset Hans Zhang
2026-05-11 4:58 ` Aksh Garg
2026-05-09 13:07 ` [PATCH v2 3/3] PCI: cadence: Use dynamic PCIe capability offset in host driver Hans Zhang
2026-05-11 4:47 ` Aksh Garg
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