From: Hans Zhang <18255117159@163.com>
To: bhelgaas@google.com, mani@kernel.org
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Hans Zhang <18255117159@163.com>
Subject: [PATCH 1/3] PCI: Add common TLP type macros and convert aspeed/mediatek
Date: Sat, 16 May 2026 23:36:55 +0800 [thread overview]
Message-ID: <20260516153657.65214-2-18255117159@163.com> (raw)
In-Reply-To: <20260516153657.65214-1-18255117159@163.com>
Introduce a set of unified TLP type macros in pci.h according to PCIe
r7.0, sec 2.2.1:
- PCIE_TLP_TYPE_MEM_RDWR (0x00) for Memory Read/Write
- PCIE_TLP_TYPE_IO_RDWR (0x02) for I/O Read/Write
- PCIE_TLP_TYPE_CFG0_RDWR (0x04) for Type 0 Config Read/Write
- PCIE_TLP_TYPE_CFG1_RDWR (0x05) for Type 1 Config Read/Write
- PCIE_TLP_TYPE_MSG (0x10) for Message Request (routing to RC)
These replace the old per-driver hardcoded values or local macros, and
also replace the previous PCIE_TLP_TYPE_CFG0_RD/WR and
PCIE_TLP_TYPE_CFG1_RD/WR definitions which had identical numeric values.
The read/write distinction is already handled by the TLP Format field
(Fmt), so a single type macro suffices.
Convert the aspeed and mediatek drivers to use the new macros, and remove
the obsolete definitions from pci.h.
No functional change intended.
Signed-off-by: Hans Zhang <18255117159@163.com>
---
drivers/pci/controller/pcie-aspeed.c | 8 ++++----
drivers/pci/controller/pcie-mediatek.c | 8 ++------
drivers/pci/pci.h | 9 +++++----
3 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/controller/pcie-aspeed.c b/drivers/pci/controller/pcie-aspeed.c
index 6acfae7d026e..9aa9e14c6148 100644
--- a/drivers/pci/controller/pcie-aspeed.c
+++ b/drivers/pci/controller/pcie-aspeed.c
@@ -127,19 +127,19 @@
#define CFG0_READ_FMTTYPE \
FIELD_PREP(ASPEED_TLP_COMMON_FIELDS, \
ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_NO_DATA, \
- PCIE_TLP_TYPE_CFG0_RD))
+ PCIE_TLP_TYPE_CFG0_RDWR))
#define CFG0_WRITE_FMTTYPE \
FIELD_PREP(ASPEED_TLP_COMMON_FIELDS, \
ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_DATA, \
- PCIE_TLP_TYPE_CFG0_WR))
+ PCIE_TLP_TYPE_CFG0_RDWR))
#define CFG1_READ_FMTTYPE \
FIELD_PREP(ASPEED_TLP_COMMON_FIELDS, \
ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_NO_DATA, \
- PCIE_TLP_TYPE_CFG1_RD))
+ PCIE_TLP_TYPE_CFG1_RDWR))
#define CFG1_WRITE_FMTTYPE \
FIELD_PREP(ASPEED_TLP_COMMON_FIELDS, \
ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_DATA, \
- PCIE_TLP_TYPE_CFG1_WR))
+ PCIE_TLP_TYPE_CFG1_RDWR))
#define CFG_PAYLOAD_SIZE 0x01 /* 1 DWORD */
#define TLP_HEADER_BYTE_EN(x, y) ((GENMASK((x) - 1, 0) << ((y) % 4)))
#define TLP_GET_VALUE(x, y, z) \
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 75722524fe74..fda4658ba9f1 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -111,10 +111,6 @@
#define APP_CFG_REQ BIT(0)
#define APP_CPL_STATUS GENMASK(7, 5)
-#define CFG_WRRD_TYPE_0 4
-#define CFG_WR_FMT 2
-#define CFG_RD_FMT 0
-
#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
@@ -295,7 +291,7 @@ static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
u32 tmp;
/* Write PCIe configuration transaction header for Cfgrd */
- writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
+ writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_NO_DATA),
port->base + PCIE_CFG_HEADER0);
writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
@@ -325,7 +321,7 @@ static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
int where, int size, u32 val)
{
/* Write PCIe configuration transaction header for Cfgwr */
- writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
+ writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_DATA),
port->base + PCIE_CFG_HEADER0);
writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4a14f88e543a..23ad51e4c434 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -71,10 +71,11 @@ struct pcie_tlp_log;
#define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */
/* Type of TLP; PCIe r7.0, sec 2.2.1 */
-#define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */
-#define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */
-#define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */
-#define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */
+#define PCIE_TLP_TYPE_MEM_RDWR 0x00 /* Memory Read/Write Request */
+#define PCIE_TLP_TYPE_IO_RDWR 0x02 /* I/O Read/Write Request */
+#define PCIE_TLP_TYPE_CFG0_RDWR 0x04 /* Config Type 0 Read/Write Request */
+#define PCIE_TLP_TYPE_CFG1_RDWR 0x05 /* Config Type 1 Read/Write Request */
+#define PCIE_TLP_TYPE_MSG 0x10 /* Message With/Without data Request */
/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
#define PCIE_MSG_TYPE_R_RC 0
--
2.34.1
next prev parent reply other threads:[~2026-05-16 15:37 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-16 15:36 [PATCH 0/3] PCI: Unify TLP type definitions across controller drivers Hans Zhang
2026-05-16 15:36 ` Hans Zhang [this message]
2026-05-16 15:36 ` [PATCH 2/3] PCI: dwc: Replace ATU type macros with common TLP type macros Hans Zhang
2026-05-16 15:36 ` [PATCH 3/3] PCI: cadence: Use " Hans Zhang
2026-06-09 13:56 ` [PATCH 0/3] PCI: Unify TLP type definitions across controller drivers Manivannan Sadhasivam
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