From: "Bowman, Terry" <terry.bowman@amd.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com,
shiju.jose@huawei.com, ming.li@zohomail.com,
Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
lukas@wunner.de, Benjamin.Cheatham@amd.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, alucerop@amd.com, ira.weiny@intel.com,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v13 08/25] CXL/AER: Move AER drivers RCH error handling into pcie/aer_cxl_rch.c
Date: Wed, 10 Dec 2025 15:57:57 -0600 [thread overview]
Message-ID: <212e35e0-3c71-443b-9f4a-8720ef3d0ba0@amd.com> (raw)
In-Reply-To: <ed865f72-8fcc-40ff-afa2-0ed895332126@amd.com>
On 12/8/2025 3:28 PM, Bowman, Terry wrote:
> On 12/8/2025 12:06 PM, Bjorn Helgaas wrote:
>> I vote for a subject like:
>>
>> PCI/AER: Move CXL RCH error handling to aer_cxl_rch.c
>>
>> I think stuff in drivers/pci should have a PCI/... prefix. "CXL" is
>> really its own major subsystem, not a feature of PCI.
>>
>> On Mon, Nov 03, 2025 at 06:09:44PM -0600, Terry Bowman wrote:
>>> The restricted CXL Host (RCH) AER error handling logic currently resides
>>> in the AER driver file, drivers/pci/pcie/aer.c. CXL specific changes are
>>> conditionally compiled using #ifdefs.
>>
>> s|the AER driver file, drivers/pci/pcie/aer.c|aer.c|
>>
>>> Improve the AER driver maintainability by separating the RCH specific logic
>>> from the AER driver's core functionality and removing the ifdefs. Introduce
>>> drivers/pci/pcie/aer_cxl_rch.c for moving the RCH AER logic into.
>>> Conditionally compile the file using the CONFIG_CXL_RCH_RAS Kconfig.
>>>
>>> Move the CXL logic into the new file but leave helper functions in aer.c
>>> for now as they will be moved in future patch for CXL virtual hierarchy
>>> handling. Export the handler functions as needed. Export
>>> pci_aer_unmask_internal_errors() allowing for all subsystems to use.
>>> Avoid multiple declaration moves and export cxl_error_is_native() now to
>>> allow access from cxl_core.
>>>
>>> Inorder to maintain compilation after the move other changes are required.
>>> Change cxl_rch_handle_error() & cxl_rch_enable_rcec() to be non-static
>>> inorder for accessing from the AER driver in aer.c.
>>
>> s/Inorder to/In order to/ (or just "To maintain ...")
>> /inorder for accessing from the AER driver in/so they can be used by/
>>
>>> Update the new file with the SPDX and 2023 AMD copyright notations because
>>> the RCH bits were initally contributed in 2023 by AMD.
>>
>> Maybe cite the commit that did this so it's easy to check.
>>
>
> Ok
>
>>> +++ b/drivers/pci/pci.h
>>
>>> +#ifdef CONFIG_CXL_RAS
>>> +bool is_internal_error(struct aer_err_info *info);
>>> +#else
>>> +static inline bool is_internal_error(struct aer_err_info *info) { return false; }
>>
>> This used to be static and internal. "is_internal_error()" seems a
>> little too generic now that it's not static; probably should include
>> "aer". Maybe rename it in a preliminary patch so the move is more of
>> a pure move.
>>
>>> +++ b/drivers/pci/pcie/aer.c
>>> @@ -1130,7 +1130,7 @@ static bool find_source_device(struct pci_dev *parent,
>>> * Note: AER must be enabled and supported by the device which must be
>>> * checked in advance, e.g. with pcie_aer_is_native().
>>> */
>>> -static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
>>> +void pci_aer_unmask_internal_errors(struct pci_dev *dev)
>>> {
>>> int aer = dev->aer_cap;
>>> u32 mask;
>>> @@ -1143,116 +1143,25 @@ static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
>>> mask &= ~PCI_ERR_COR_INTERNAL;
>>> pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
>>> }
>>> +EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors);
>>
>> Not sure why these EXPORTs are needed. Is there a caller that can be
>> a module? The callers I see look like they would be builtin. If you
>> add callers later that need this, the export can be done then.
>>
>
> pci_aer_unmask_internal_errors() is called by the cxl_core module later in
> the 2nd to-last patch. I'll move the export change to the later patch. At
> one point I was trying to avoid changes to same definitions multiple times.
>
>>> +++ b/include/linux/aer.h
>>> @@ -56,12 +56,20 @@ struct aer_capability_regs {
>>> #if defined(CONFIG_PCIEAER)
>>> int pci_aer_clear_nonfatal_status(struct pci_dev *dev);
>>> int pcie_aer_is_native(struct pci_dev *dev);
>>> +void pci_aer_unmask_internal_errors(struct pci_dev *dev);
>>> #else
>>> static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
>>> {
>>> return -EINVAL;
>>> }
>>> static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
>>> +static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }
>>> +#endif
>>> +
>>> +#ifdef CONFIG_CXL_RAS
>>> +bool cxl_error_is_native(struct pci_dev *dev);
>>> +#else
>>> +static inline bool cxl_error_is_native(struct pci_dev *dev) { return false; }
>>
>> These include/linux/aer.h changes look like a separate patch. Moving
>> code from aer.c to aer_cxl_rch.c doesn't add any callers outside
>> drivers/pci, so these shouldn't need to be in include/linux/.
>
> I'll remove these from here.
>
> - Terry
Hi Bjorn,
I reviewed this more closely and recalled the reasoning behind the change.
Lukas requested that pci_aer_unmask_internal_errors() be made available
across the entire kernel. I already noted this in the commit message, but
I can also include a link to Lukas’s request. Alternatively, I could split
this into a separate patch with a Recommended-by tag, leave it as is, or
make another adjustment. Additionally, I’ll update cxl_error_is_native()
so it’s only included when necessary.
Terry
next prev parent reply other threads:[~2025-12-10 21:58 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 0:09 [PATCH v13 00/25] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-11-04 0:09 ` [PATCH v13 01/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-12-06 0:31 ` Bjorn Helgaas
2025-12-06 0:41 ` dan.j.williams
2025-12-06 1:56 ` Bjorn Helgaas
2025-12-06 4:56 ` dan.j.williams
2025-11-04 0:09 ` [PATCH v13 02/25] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-12-06 0:45 ` Bjorn Helgaas
2025-12-08 15:26 ` Bowman, Terry
2025-12-08 18:33 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 03/25] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-11-04 0:09 ` [PATCH v13 04/25] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-11-04 0:09 ` [PATCH v13 05/25] cxl: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Terry Bowman
2025-11-04 0:09 ` [PATCH v13 06/25] cxl: Move CXL driver's RCH error handling into core/ras_rch.c Terry Bowman
2025-11-04 0:09 ` [PATCH v13 07/25] CXL/AER: Replace device_lock() in cxl_rch_handle_error_iter() with guard() lock Terry Bowman
2025-12-08 18:05 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 08/25] CXL/AER: Move AER drivers RCH error handling into pcie/aer_cxl_rch.c Terry Bowman
2025-12-08 18:06 ` Bjorn Helgaas
2025-12-08 21:28 ` Bowman, Terry
2025-12-10 21:57 ` Bowman, Terry [this message]
2025-12-10 23:12 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 09/25] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-11-04 0:09 ` [PATCH v13 10/25] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-11-04 0:09 ` [PATCH v13 11/25] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-11-04 0:09 ` [PATCH v13 12/25] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-11-04 0:09 ` [PATCH v13 13/25] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-11-04 0:09 ` [PATCH v13 14/25] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-11-04 0:09 ` [PATCH v13 15/25] CXL/PCI: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2025-11-04 0:09 ` [PATCH v13 16/25] CXL/AER: Introduce pcie/aer_cxl_vh.c in AER driver for forwarding CXL errors Terry Bowman
2025-12-08 18:36 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 17/25] cxl: Introduce cxl_pci_drv_bound() to check for bound driver Terry Bowman
2025-11-04 0:09 ` [PATCH v13 18/25] cxl: Change CXL handlers to use guard() instead of scoped_guard() Terry Bowman
2025-11-04 0:09 ` [PATCH v13 19/25] cxl/pci: Introduce CXL protocol error handlers for Endpoints Terry Bowman
2025-11-04 0:09 ` [PATCH v13 20/25] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-12-08 18:37 ` Bjorn Helgaas
2025-12-09 15:17 ` Bowman, Terry
2025-11-04 0:09 ` [PATCH v13 21/25] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-11-04 0:09 ` [PATCH v13 22/25] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-12-08 18:38 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=212e35e0-3c71-443b-9f4a-8720ef3d0ba0@amd.com \
--to=terry.bowman@amd.com \
--cc=Benjamin.Cheatham@amd.com \
--cc=PradeepVineshReddy.Kodamati@amd.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=alison.schofield@intel.com \
--cc=alucerop@amd.com \
--cc=bhelgaas@google.com \
--cc=dan.carpenter@linaro.org \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=helgaas@kernel.org \
--cc=ira.weiny@intel.com \
--cc=jonathan.cameron@huawei.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lukas@wunner.de \
--cc=ming.li@zohomail.com \
--cc=rrichter@amd.com \
--cc=sathyanarayanan.kuppuswamy@linux.intel.com \
--cc=shiju.jose@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).