From: Manivannan Sadhasivam <mani@kernel.org>
To: Johannes Erdfelt <johannes@erdfelt.com>,
Aurelien Jarno <aurelien@aurel32.net>
Cc: Alex Elder <elder@riscstar.com>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, vkoul@kernel.org, kishon@kernel.org,
dlan@gentoo.org, guodong@riscstar.com, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
p.zabel@pengutronix.de, christian.bruel@foss.st.com,
shradha.t@samsung.com, krishna.chundru@oss.qualcomm.com,
qiang.yu@oss.qualcomm.com, namcao@linutronix.de,
thippeswamy.havalige@amd.com, inochiama@gmail.com,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, spacemit@lists.linux.dev,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller
Date: Thu, 30 Oct 2025 22:11:12 +0530 [thread overview]
Message-ID: <5kwbaj2eqr4imcaoh6otqo7huuraqhodxh4dbwc33vqpi5j5yq@ueufnqetrg2m> (raw)
In-Reply-To: <20251028204832.GN15521@sventech.com>
+ Aurelien
On Tue, Oct 28, 2025 at 01:48:32PM -0700, Johannes Erdfelt wrote:
> On Tue, Oct 28, 2025, Alex Elder <elder@riscstar.com> wrote:
> > On 10/28/25 1:42 PM, Johannes Erdfelt wrote:
> > > I have been testing this patchset recently as well, but on an Orange Pi
> > > RV2 board instead (and an extra RV2 specific patch to enable power to
> > > the M.2 slot).
> > >
> > > I ran into the same symptoms you had ("QID 0 timeout" after about 60
> > > seconds). However, I'm using an Intel 600p. I can confirm my NVME drive
> > > seems to work fine with the "pcie_aspm=off" workaround as well.
> >
> > I don't see this problem, and haven't tried to reproduce it yet.
> >
> > Mani told me I needed to add these lines to ensure the "runtime
> > PM hierarchy of PCIe chain" won't be "broken":
> >
> > pm_runtime_set_active()
> > pm_runtime_no_callbacks()
> > devm_pm_runtime_enable()
> >
> > Just out of curiosity, could you try with those lines added
> > just before these assignments in k1_pcie_probe()?
> >
> > k1->pci.dev = dev;
> > k1->pci.ops = &k1_pcie_ops;
> > dw_pcie_cap_set(&k1->pci, REQ_RES);
> >
> > I doubt it will fix what you're seeing, but at the moment I'm
> > working on something else.
>
> Unfortunately there is no difference with the runtime PM hierarchy
> additions.
>
These are not supposed to fix the issues you were facing. I discussed with Alex
offline and figured out that L1 works fine on his BPI-F3 board with a NVMe SSD.
And I believe, Aurelien is also using that same board, but with different
SSDs. But what is puzzling me is, L1 is breaking Aurelien's setup with 3 SSDs
from different vendors. It apparently works fine on Alex's setup. So it somehow
confirms that Root Port supports and behaves correctly with L1. But at the same
time, I cannot just say without evidence that L1 is broken on all these SSDs
that you and Aurelien tested with.
So until that is figured out, I've asked Alex to disable L1 CAP in the
controller driver. So in the next version of this series, your SSDs should work
out of the box.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2025-10-30 16:41 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 15:35 [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller Alex Elder
2025-10-13 15:35 ` [PATCH v2 1/7] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo PHY Alex Elder
2025-10-15 14:52 ` Rob Herring
2025-10-17 16:20 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 2/7] dt-bindings: phy: spacemit: introduce PCIe PHY Alex Elder
2025-10-15 16:41 ` Rob Herring (Arm)
2025-10-17 16:20 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller Alex Elder
2025-10-14 1:55 ` Yao Zi
2025-10-14 1:57 ` Alex Elder
2025-10-15 16:47 ` Rob Herring
2025-10-17 16:20 ` Alex Elder
2025-10-26 16:38 ` Manivannan Sadhasivam
2025-10-27 22:24 ` Alex Elder
2025-10-28 5:58 ` Manivannan Sadhasivam
2025-10-30 0:10 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 4/7] phy: spacemit: introduce PCIe/combo PHY Alex Elder
2025-10-15 21:51 ` Aurelien Jarno
2025-10-17 16:21 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 5/7] PCI: spacemit: introduce SpacemiT PCIe host driver Alex Elder
2025-10-26 16:55 ` Manivannan Sadhasivam
2025-10-27 22:24 ` Alex Elder
2025-10-28 7:06 ` Manivannan Sadhasivam
2025-10-30 0:10 ` Alex Elder
2025-10-31 6:05 ` Manivannan Sadhasivam
2025-10-31 13:38 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 6/7] riscv: dts: spacemit: add a PCIe regulator Alex Elder
2025-10-13 15:35 ` [PATCH v2 7/7] riscv: dts: spacemit: PCIe and PHY-related updates Alex Elder
2025-10-16 16:47 ` [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller Aurelien Jarno
2025-10-17 16:21 ` Alex Elder
2025-10-28 17:59 ` Aurelien Jarno
2025-10-28 18:42 ` Johannes Erdfelt
2025-10-28 19:10 ` Alex Elder
2025-10-28 20:48 ` Johannes Erdfelt
2025-10-28 20:49 ` Alex Elder
2025-10-30 16:41 ` Manivannan Sadhasivam [this message]
2025-10-30 17:49 ` Aurelien Jarno
2025-10-31 6:10 ` Manivannan Sadhasivam
2025-11-03 16:42 ` Alex Elder
2025-10-28 21:08 ` Aurelien Jarno
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