From: Dan Williams <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Cc: <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<Jonathan.Cameron@huawei.com>, <dave@stgolabs.net>,
<bhelgaas@google.com>, <lukas@wunner.de>
Subject: Re: [PATCH v5 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders
Date: Wed, 1 May 2024 19:55:39 -0700 [thread overview]
Message-ID: <663300ab61745_138462945@dwillia2-mobl3.amr.corp.intel.com.notmuch> (raw)
In-Reply-To: <20240429223610.1341811-5-dave.jiang@intel.com>
Dave Jiang wrote:
> SBR is equivalent to a device been hot removed and inserted again. Doing a
> SBR on a CXL type 3 device is problematic if the exported device memory is
> part of system memory that cannot be offlined. The event is equivalent to
> violently ripping out that range of memory from the kernel. While the
> hardware requires the "Unmask SBR" bit set in the Port Control Extensions
> register and the kernel currently does not unmask it, user can unmask
> this bit via setpci or similar tool.
>
> The driver does not have a way to detect whether a reset coming from the
> PCI subsystem is a Function Level Reset (FLR) or SBR. The only way to
> detect is to note if a decoder is marked as enabled in software but the
> decoder control register indicates it's not committed.
>
> A helper function is added to find discrepancy between the decoder
> software state versus the hardware register state.
>
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v5:
> - Simplify retrieving of cxld. (Dan)
> - Add lock to device to prevent racing disabled cxlmd. (Dan)
> - Promote dev_warn() to dev_crit(). (Dan)
> - Move LOCKDEP_NOW_UNRELIABLE to LOCKDEP_IS_OK. (Dan)
Yup, all of those got addressed:
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
prev parent reply other threads:[~2024-05-02 2:55 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-29 22:35 [PATCH v5 0/4] PCI: Add Secondary Bus Reset (SBR) support for CXL Dave Jiang
2024-04-29 22:35 ` [PATCH v5 1/4] PCI/cxl: Move PCI CXL vendor Id to a common location from CXL subsystem Dave Jiang
2024-05-01 15:37 ` PJ Waskiewicz
2024-05-01 16:04 ` Dave Jiang
2024-05-01 16:09 ` Dan Williams
2024-04-29 22:35 ` [PATCH v5 2/4] PCI: Add check for CXL Secondary Bus Reset Dave Jiang
2024-05-01 19:47 ` Dan Williams
2024-04-29 22:35 ` [PATCH v5 3/4] PCI: Create new reset method to force SBR for CXL Dave Jiang
2024-05-02 2:51 ` Dan Williams
2024-04-29 22:35 ` [PATCH v5 4/4] cxl: Add post reset warning if reset results in loss of previously committed HDM decoders Dave Jiang
2024-05-02 2:55 ` Dan Williams [this message]
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