From: mr.nuke.me@gmail.com
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-phy@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v3 6/7] phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY
Date: Mon, 15 Apr 2024 16:25:48 -0500 [thread overview]
Message-ID: <6726fa2b-f5fe-10fb-6aab-f76d61f0b3cd@gmail.com> (raw)
In-Reply-To: <CAA8EJpqY1aDZMaeqBULEOD26UeGYbLd8RsA16jZw7zXJ7_oGPQ@mail.gmail.com>
On 4/15/24 15:10, Dmitry Baryshkov wrote:
> On Mon, 15 Apr 2024 at 21:23, Alexandru Gagniuc <mr.nuke.me@gmail.com> wrote:
>>
>> Add support for the gen3x2 PCIe PHY on IPQ9574, ported form downstream
>> 5.4 kernel. Only the serdes and pcs_misc tables are new, the others
>> being reused from IPQ8074 and IPQ6018 PHYs.
>>
>> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 +++++++++++++++++-
>> .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++
>> 2 files changed, 149 insertions(+), 1 deletion(-)
>>
>
> [skipped]
>
>> @@ -2448,7 +2542,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
>>
>> /* list of clocks required by phy */
>> static const char * const qmp_pciephy_clk_l[] = {
>> - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
>> + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "anoc", "snoc"
>
> Are the NoC clocks really necessary to drive the PHY? I think they are
> usually connected to the controllers, not the PHYs.
The system will hang if these clocks are not enabled. They are also
attached to the PHY in the QCA 5.4 downstream kernel.
>> };
>>
>> /* list of regulators */
>> @@ -2499,6 +2593,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
>> .rx = 0x0400,
>> };
>>
>> +static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {
>> + .serdes = 0,
>> + .pcs = 0x1000,
>> + .pcs_misc = 0x1400,
>> + .tx = 0x0200,
>> + .rx = 0x0400,
>> + .tx2 = 0x0600,
>> + .rx2 = 0x0800,
>> +};
>> +
>> static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
>> .serdes = 0,
>> .pcs = 0x0a00,
>> @@ -2728,6 +2832,33 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
>> .phy_status = PHYSTATUS,
>> };
>>
>> +static const struct qmp_phy_cfg ipq9574_pciephy_gen3x2_cfg = {
>> + .lanes = 2,
>> +
>> + .offsets = &qmp_pcie_offsets_ipq9574,
>> +
>> + .tbls = {
>> + .serdes = ipq9574_gen3x2_pcie_serdes_tbl,
>> + .serdes_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),
>> + .tx = ipq8074_pcie_gen3_tx_tbl,
>> + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
>> + .rx = ipq6018_pcie_rx_tbl,
>> + .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
>> + .pcs = ipq6018_pcie_pcs_tbl,
>> + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
>> + .pcs_misc = ipq9574_gen3x2_pcie_pcs_misc_tbl,
>> + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),
>> + },
>> + .reset_list = ipq8074_pciephy_reset_l,
>> + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
>> + .vreg_list = NULL,
>> + .num_vregs = 0,
>> + .regs = pciephy_v4_regs_layout,
>
> So, is it v4 or v5?
Please give me a day or so to go over my notes and give you a more
coherent explanation of why this versioning was chosen. I am only
working from the QCA 5.4 downstream sources. I don't have any
documentation for the silicon
Alex
>
>> +
>> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
>> + .phy_status = PHYSTATUS,
>> +};
>> +
>> static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
>> .lanes = 2,
>>
>
>
>
> --
> With best wishes
> Dmitry
next prev parent reply other threads:[~2024-04-15 21:25 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-15 18:20 [PATCH v3 0/7] ipq9574: Enable PCI-Express support Alexandru Gagniuc
2024-04-15 18:20 ` [PATCH v3 1/7] dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 Alexandru Gagniuc
2024-04-15 18:20 ` [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Alexandru Gagniuc
2024-04-15 20:04 ` Dmitry Baryshkov
2024-04-19 22:22 ` Stephen Boyd
2024-04-15 18:20 ` [PATCH v3 3/7] dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller Alexandru Gagniuc
2024-04-18 12:59 ` Rob Herring
2024-04-15 18:20 ` [PATCH v3 4/7] PCI: qcom: Add support for IPQ9574 Alexandru Gagniuc
2024-04-15 20:04 ` Dmitry Baryshkov
2024-04-15 20:07 ` mr.nuke.me
2024-04-17 7:06 ` Manivannan Sadhasivam
2024-04-19 19:44 ` mr.nuke.me
2024-04-22 7:11 ` Manivannan Sadhasivam
2024-04-17 7:14 ` Manivannan Sadhasivam
2024-04-15 18:20 ` [PATCH v3 5/7] dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY Alexandru Gagniuc
2024-04-18 13:00 ` Rob Herring
2024-04-15 18:20 ` [PATCH v3 6/7] phy: qcom-qmp-pcie: add support for " Alexandru Gagniuc
2024-04-15 20:10 ` Dmitry Baryshkov
2024-04-15 21:25 ` mr.nuke.me [this message]
2024-04-16 21:25 ` Alex G.
2024-04-16 21:50 ` Dmitry Baryshkov
2024-04-29 6:20 ` Varadarajan Narayanan
2024-04-29 10:55 ` Dmitry Baryshkov
2024-04-30 6:31 ` Varadarajan Narayanan
2024-04-30 21:51 ` mr.nuke.me
2024-04-30 21:59 ` Dmitry Baryshkov
2024-04-15 18:20 ` [PATCH v3 7/7] arm64: dts: qcom: ipq9574: add PCIe2 nodes Alexandru Gagniuc
2024-04-17 7:34 ` Manivannan Sadhasivam
2024-04-18 15:33 ` mr.nuke.me
2024-04-22 7:10 ` Manivannan Sadhasivam
2024-04-22 14:29 ` Konrad Dybcio
2024-04-19 14:28 ` [PATCH v3 0/7] ipq9574: Enable PCI-Express support Kathiravan Thirumoorthy
2024-04-19 19:47 ` mr.nuke.me
2024-04-23 6:11 ` Kathiravan Thirumoorthy
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