From: <dan.j.williams@intel.com>
To: Bjorn Helgaas <helgaas@kernel.org>, <dan.j.williams@intel.com>
Cc: Terry Bowman <terry.bowman@amd.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <bhelgaas@google.com>,
<shiju.jose@huawei.com>, <ming.li@zohomail.com>,
<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,
<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,
<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <alucerop@amd.com>,
<ira.weiny@intel.com>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Subject: Re: [PATCH v13 01/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h
Date: Fri, 5 Dec 2025 20:56:52 -0800 [thread overview]
Message-ID: <6933b7946874f_1b2e10067@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20251206015613.GA3303517@bhelgaas>
Bjorn Helgaas wrote:
> On Fri, Dec 05, 2025 at 04:41:40PM -0800, dan.j.williams@intel.com wrote:
> > Bjorn Helgaas wrote:
> > > On Mon, Nov 03, 2025 at 06:09:37PM -0600, Terry Bowman wrote:
> > > > The CXL DVSECs are currently defined in cxl/core/cxlpci.h. These are not
> > > > accessible to other subsystems. Move these to uapi/linux/pci_regs.h.
>
> > > > +#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20)
> > >
> > > Looks like a functional duplicate of PCI_DVSEC_HEADER1_LEN().
> > >
> > > Why __GENMASK() instead of GENMASK()? I don't know the purpose of
> > > __GENMASK(), but I see other include/uapi/ files using GENMASK().
> > > Maybe they're wrong?
> > >
> > > Same questions for _BITUL() below.
> >
> > See this commit:
> >
> > 3c7a8e190bc5 uapi: introduce uapi-friendly macros for GENMASK
> >
> > GENMASK() for a long time was not available to uapi headers since uapi
> > headers can only include other include/uapi/ headers, not
> > include/linux/. That commit made some common kernel bitfield helpers
> > finally available to the uapi side of the house.
>
> So are the uses I see here wrong?
>
> git grep "\<GENMASK\|\<BIT\>" include/uapi/
Yes, but the build failure for userspace can be mitigated if it provides
a replacement defintion. For example, the project for CXL
user tooling locally defines:
util/bitmap.h:34:#define BIT(nr) (1UL << (nr))
util/bitmap.h:31:#define GENMASK(h, l) \
...to supplement the missing kernel definitions, but those predated
2023. Paolo solved the problem globally with 3c7a8e190bc5.
Otherwise, userspace projects that do not already locally define
GENMASK() but include uapi/pci_regs.h would start seeing new build
failures when they update kernel headers.
next prev parent reply other threads:[~2025-12-06 4:57 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 0:09 [PATCH v13 00/25] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-11-04 0:09 ` [PATCH v13 01/25] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-12-06 0:31 ` Bjorn Helgaas
2025-12-06 0:41 ` dan.j.williams
2025-12-06 1:56 ` Bjorn Helgaas
2025-12-06 4:56 ` dan.j.williams [this message]
2025-11-04 0:09 ` [PATCH v13 02/25] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-12-06 0:45 ` Bjorn Helgaas
2025-12-08 15:26 ` Bowman, Terry
2025-12-08 18:33 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 03/25] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-11-04 0:09 ` [PATCH v13 04/25] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-11-04 0:09 ` [PATCH v13 05/25] cxl: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c Terry Bowman
2025-11-04 0:09 ` [PATCH v13 06/25] cxl: Move CXL driver's RCH error handling into core/ras_rch.c Terry Bowman
2025-11-04 0:09 ` [PATCH v13 07/25] CXL/AER: Replace device_lock() in cxl_rch_handle_error_iter() with guard() lock Terry Bowman
2025-12-08 18:05 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 08/25] CXL/AER: Move AER drivers RCH error handling into pcie/aer_cxl_rch.c Terry Bowman
2025-12-08 18:06 ` Bjorn Helgaas
2025-12-08 21:28 ` Bowman, Terry
2025-12-10 21:57 ` Bowman, Terry
2025-12-10 23:12 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 09/25] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-11-04 0:09 ` [PATCH v13 10/25] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-11-04 0:09 ` [PATCH v13 11/25] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-11-04 0:09 ` [PATCH v13 12/25] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-11-04 0:09 ` [PATCH v13 13/25] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-11-04 0:09 ` [PATCH v13 14/25] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-11-04 0:09 ` [PATCH v13 15/25] CXL/PCI: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2025-11-04 0:09 ` [PATCH v13 16/25] CXL/AER: Introduce pcie/aer_cxl_vh.c in AER driver for forwarding CXL errors Terry Bowman
2025-12-08 18:36 ` Bjorn Helgaas
2025-11-04 0:09 ` [PATCH v13 17/25] cxl: Introduce cxl_pci_drv_bound() to check for bound driver Terry Bowman
2025-11-04 0:09 ` [PATCH v13 18/25] cxl: Change CXL handlers to use guard() instead of scoped_guard() Terry Bowman
2025-11-04 0:09 ` [PATCH v13 19/25] cxl/pci: Introduce CXL protocol error handlers for Endpoints Terry Bowman
2025-11-04 0:09 ` [PATCH v13 20/25] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-12-08 18:37 ` Bjorn Helgaas
2025-12-09 15:17 ` Bowman, Terry
2025-11-04 0:09 ` [PATCH v13 21/25] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-11-04 0:09 ` [PATCH v13 22/25] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-12-08 18:38 ` Bjorn Helgaas
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