From: Shawn Lin <shawn.lin@rock-chips.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: shawn.lin@rock-chips.com, Bjorn Helgaas <helgaas@kernel.org>,
linux-pci@vger.kernel.org,
Christian Zigotzky <chzigotzky@xenosoft.de>,
mad skateman <madskateman@gmail.com>,
"R . T . Dickinson" <rtd2@xtra.co.nz>,
Darren Stevens <darren@stevens-zone.net>,
John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>,
Lukas Wunner <lukas@wunner.de>,
luigi burdo <intermediadc@hotmail.com>, Al <al@datazap.net>,
Roland <rol7and@gmx.com>, Hongxing Zhu <hongxing.zhu@nxp.com>,
hypexed@yahoo.com.au, linuxppc-dev@lists.ozlabs.org,
debian-powerpc@lists.debian.org, linux-kernel@vger.kernel.org,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH 1/2] PCI/ASPM: Cache Link Capabilities so quirks can override them
Date: Fri, 7 Nov 2025 14:16:02 +0800 [thread overview]
Message-ID: <a46b93b6-b5ea-46d1-95df-de0333a24124@rock-chips.com> (raw)
In-Reply-To: <6fni6w6aolqgxazmepiw2clwjq54yt76pjswx7zmdgebj4svqz@mggk4qyhdrrt>
在 2025/11/07 星期五 14:03, Manivannan Sadhasivam 写道:
> On Fri, Nov 07, 2025 at 09:17:09AM +0800, Shawn Lin wrote:
>> 在 2025/11/07 星期五 2:36, Bjorn Helgaas 写道:
>>> From: Bjorn Helgaas <bhelgaas@google.com>
>>>
>>> Cache the PCIe Link Capabilities register in struct pci_dev so quirks can
>>> remove features to avoid hardware defects. The idea is:
>>>
>>> - set_pcie_port_type() reads PCIe Link Capabilities and caches it in
>>> dev->lnkcap
>>>
>>> - HEADER quirks can update the cached dev->lnkcap to remove advertised
>>> features that don't work correctly
>>>
>>> - pcie_aspm_cap_init() relies on dev->lnkcap and ignores any features not
>>> advertised there
>>>
>>
>> Quick test with a NVMe shows it works.
>>
>> Before this patch, lspci -vvv dumps:
>>
>> LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
>> ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
>> LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
>>
>>
>> Capabilities: [21c v1] L1 PM Substates
>> L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
>> L1_PM_Substates+
>> PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
>> L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
>> T_CommonMode=0us LTR1.2_Threshold=26016ns
>>
>> After this patch + a local quirk patch like your patch 2, it shows:
>>
>> LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
>> ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
>> LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk-
>>
>> Capabilities: [21c v1] L1 PM Substates
>> L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
>> L1_PM_Substates+
>> PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
>> L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
>> T_CommonMode=0us LTR1.2_Threshold=0ns
>>
>>
>>
>> One things I noticed is CommClk in LnkCtl is changed.
>
> That's not because of this series, but because of your quirk that disables L0s
> and L1. Common Clock Configuration happens only when ASPM is enabled, if it is
> disabled, PCI core will not configure it (the value remains untouched). That's
> why it was enabled before your quirk and disabled afterwards.
>
Thanks for the detailed explanation, I have no more questions now.
> This bit is also only used to report the L0s and L1 Exit latencies by the
> devices.
>
> - Mani
>
next prev parent reply other threads:[~2025-11-07 6:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-06 18:36 [PATCH 0/2] PCI/ASPM: Allow quirks to avoid L0s and L1 Bjorn Helgaas
2025-11-06 18:36 ` [PATCH 1/2] PCI/ASPM: Cache Link Capabilities so quirks can override them Bjorn Helgaas
2025-11-07 1:17 ` Shawn Lin
2025-11-07 6:03 ` Manivannan Sadhasivam
2025-11-07 6:16 ` Shawn Lin [this message]
2025-11-07 5:32 ` Lukas Wunner
2025-11-07 15:25 ` Bjorn Helgaas
2025-11-06 18:36 ` [PATCH 2/2] PCI/ASPM: Avoid L0s and L1 on Freescale Root Ports Bjorn Helgaas
2025-11-07 5:35 ` Lukas Wunner
2025-11-07 6:09 ` Manivannan Sadhasivam
2025-11-07 21:55 ` Bjorn Helgaas
2025-11-06 23:45 ` [PATCH 0/2] PCI/ASPM: Allow quirks to avoid L0s and L1 Bjorn Helgaas
2025-11-07 2:33 ` Hongxing Zhu
2025-11-07 5:40 ` Manivannan Sadhasivam
2025-11-07 6:33 ` Lukas Wunner
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