From: Manivannan Sadhasivam <mani@kernel.org>
To: Alex Elder <elder@riscstar.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, vkoul@kernel.org, kishon@kernel.org,
dlan@gentoo.org, guodong@riscstar.com, pjw@kernel.org,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
p.zabel@pengutronix.de, christian.bruel@foss.st.com,
shradha.t@samsung.com, krishna.chundru@oss.qualcomm.com,
qiang.yu@oss.qualcomm.com, namcao@linutronix.de,
thippeswamy.havalige@amd.com, inochiama@gmail.com,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, spacemit@lists.linux.dev,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller
Date: Tue, 28 Oct 2025 11:28:40 +0530 [thread overview]
Message-ID: <tjnc4wwpdwlziboonlmki6nm7t523k5atemygwyg7ck5knsde4@anjrtcf5gcq7> (raw)
In-Reply-To: <ae92d3f4-5131-46be-b9b1-e8ec437c9ae9@riscstar.com>
On Mon, Oct 27, 2025 at 05:24:33PM -0500, Alex Elder wrote:
> On 10/26/25 11:38 AM, Manivannan Sadhasivam wrote:
> > On Mon, Oct 13, 2025 at 10:35:20AM -0500, Alex Elder wrote:
> > > Add the Device Tree binding for the PCIe root complex found on the
> > > SpacemiT K1 SoC. This device is derived from the Synopsys Designware
> > > PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
> > > link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
> > > typically used to support a USB 3 port.
> > >
> > > Signed-off-by: Alex Elder <elder@riscstar.com>
> > > ---
> > > v2: - Renamed the binding, using "host controller"
> > > - Added '>' to the description, and reworded it a bit
> > > - Added reference to /schemas/pci/snps,dw-pcie.yaml
> > > - Fixed and renamed the compatible string
> > > - Renamed the PMU property, and fixed its description
> > > - Consistently omit the period at the end of descriptions
> > > - Renamed the "global" clock to be "phy"
> > > - Use interrupts rather than interrupts-extended, and name the
> > > one interrupt "msi" to make clear its purpose
> > > - Added a vpcie3v3-supply property
> > > - Dropped the max-link-speed property
> > > - Changed additionalProperties to unevaluatedProperties
> > > - Dropped the label and status property from the example
> > >
> > > .../bindings/pci/spacemit,k1-pcie-host.yaml | 156 ++++++++++++++++++
> > > 1 file changed, 156 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> > > new file mode 100644
> > > index 0000000000000..87745d49c53a1
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> > > @@ -0,0 +1,156 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: SpacemiT K1 PCI Express Host Controller
> > > +
> > > +maintainers:
> > > + - Alex Elder <elder@riscstar.com>
> > > +
> > > +description: >
> > > + The SpacemiT K1 SoC PCIe host controller is based on the Synopsys
> > > + DesignWare PCIe IP. The controller uses the DesignWare built-in
> > > + MSI interrupt controller, and supports 256 MSIs.
> > > +
> > > +allOf:
> > > + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> > > +
> > > +properties:
> > > + compatible:
> > > + const: spacemit,k1-pcie
> > > +
> > > + reg:
> > > + items:
> > > + - description: DesignWare PCIe registers
> > > + - description: ATU address space
> > > + - description: PCIe configuration space
> > > + - description: Link control registers
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: dbi
> > > + - const: atu
> > > + - const: config
> > > + - const: link
> > > +
> > > + spacemit,apmu:
> > > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > > + description:
> > > + A phandle that refers to the APMU system controller, whose
> > > + regmap is used in managing resets and link state, along with
> > > + and offset of its reset control register.
> > > + items:
> > > + - items:
> > > + - description: phandle to APMU system controller
> > > + - description: register offset
> > > +
> > > + clocks:
> > > + items:
> > > + - description: DWC PCIe Data Bus Interface (DBI) clock
> > > + - description: DWC PCIe application AXI-bus master interface clock
> > > + - description: DWC PCIe application AXI-bus slave interface clock
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: dbi
> > > + - const: mstr
> > > + - const: slv
> > > +
> > > + resets:
> > > + items:
> > > + - description: DWC PCIe Data Bus Interface (DBI) reset
> > > + - description: DWC PCIe application AXI-bus master interface reset
> > > + - description: DWC PCIe application AXI-bus slave interface reset
> > > + - description: Global reset; must be deasserted for PHY to function
> > > +
> > > + reset-names:
> > > + items:
> > > + - const: dbi
> > > + - const: mstr
> > > + - const: slv
> > > + - const: phy
> > > +
> > > + interrupts:
> > > + items:
> > > + - description: Interrupt used for MSIs
> > > +
> > > + interrupt-names:
> > > + const: msi
> > > +
> > > + phys:
> > > + maxItems: 1
> > > +
> > > + vpcie3v3-supply:
> > > + description:
> > > + A phandle for 3.3v regulator to use for PCIe
> >
> > Could you please move these Root Port specific properties (phy, vpcie3v3-supply)
> > to the Root Port node?
> >
> > Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>
> OK, I'll try to follow what that ST binding does (and the
> matching driver).
>
> > For handling the 'vpcie3v3-supply', you can rely on PCI_PWRCTRL_SLOT driver.
> I looked at the code under pci/pwrctrl. But is there some other
> documentation I should be looking at for this?
>
Sorry, nothing available atm. But I will create one, once we fix some core
issues with pwrctrl so that it becomes useable for all (more in the driver
patch).
> It looks like it involves creating a new node compatible with
> "pciclass,0604". And that the purpose of that driver was to
> ensure certain resources are enabled before the "real" PCI
> device gets probed.
>
> I see two arm64 DTS files using it: x1e80100.dtsi and r8a779g0.dtsi.
> Both define this node inside the main PCIe controller node.
>
> Will this model (with the parent pwrctrl node and child PCI
> controller node) be used for all PCI controllers from here on?
>
The PCI controller (host bridge) node is the parent and the Root Port node
(which gets bind to pwrctrl slot driver) will be the child.
> Or are you saying this properly represents the relationship of
> the supply with the PCIe port in this SpacemiT case?
>
We want to use this for all the new platforms and also try to convert the old
ones too gradually.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2025-10-28 5:58 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 15:35 [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller Alex Elder
2025-10-13 15:35 ` [PATCH v2 1/7] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo PHY Alex Elder
2025-10-15 14:52 ` Rob Herring
2025-10-17 16:20 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 2/7] dt-bindings: phy: spacemit: introduce PCIe PHY Alex Elder
2025-10-15 16:41 ` Rob Herring (Arm)
2025-10-17 16:20 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller Alex Elder
2025-10-14 1:55 ` Yao Zi
2025-10-14 1:57 ` Alex Elder
2025-10-15 16:47 ` Rob Herring
2025-10-17 16:20 ` Alex Elder
2025-10-26 16:38 ` Manivannan Sadhasivam
2025-10-27 22:24 ` Alex Elder
2025-10-28 5:58 ` Manivannan Sadhasivam [this message]
2025-10-30 0:10 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 4/7] phy: spacemit: introduce PCIe/combo PHY Alex Elder
2025-10-15 21:51 ` Aurelien Jarno
2025-10-17 16:21 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 5/7] PCI: spacemit: introduce SpacemiT PCIe host driver Alex Elder
2025-10-26 16:55 ` Manivannan Sadhasivam
2025-10-27 22:24 ` Alex Elder
2025-10-28 7:06 ` Manivannan Sadhasivam
2025-10-30 0:10 ` Alex Elder
2025-10-31 6:05 ` Manivannan Sadhasivam
2025-10-31 13:38 ` Alex Elder
2025-10-13 15:35 ` [PATCH v2 6/7] riscv: dts: spacemit: add a PCIe regulator Alex Elder
2025-10-13 15:35 ` [PATCH v2 7/7] riscv: dts: spacemit: PCIe and PHY-related updates Alex Elder
2025-10-16 16:47 ` [PATCH v2 0/7] Introduce SpacemiT K1 PCIe phy and host controller Aurelien Jarno
2025-10-17 16:21 ` Alex Elder
2025-10-28 17:59 ` Aurelien Jarno
2025-10-28 18:42 ` Johannes Erdfelt
2025-10-28 19:10 ` Alex Elder
2025-10-28 20:48 ` Johannes Erdfelt
2025-10-28 20:49 ` Alex Elder
2025-10-30 16:41 ` Manivannan Sadhasivam
2025-10-30 17:49 ` Aurelien Jarno
2025-10-31 6:10 ` Manivannan Sadhasivam
2025-11-03 16:42 ` Alex Elder
2025-10-28 21:08 ` Aurelien Jarno
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=tjnc4wwpdwlziboonlmki6nm7t523k5atemygwyg7ck5knsde4@anjrtcf5gcq7 \
--to=mani@kernel.org \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=bhelgaas@google.com \
--cc=christian.bruel@foss.st.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dlan@gentoo.org \
--cc=elder@riscstar.com \
--cc=guodong@riscstar.com \
--cc=inochiama@gmail.com \
--cc=kishon@kernel.org \
--cc=krishna.chundru@oss.qualcomm.com \
--cc=krzk+dt@kernel.org \
--cc=kwilczynski@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux-riscv@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=namcao@linutronix.de \
--cc=p.zabel@pengutronix.de \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
--cc=qiang.yu@oss.qualcomm.com \
--cc=robh@kernel.org \
--cc=shradha.t@samsung.com \
--cc=spacemit@lists.linux.dev \
--cc=thippeswamy.havalige@amd.com \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).