From: Manivannan Sadhasivam <mani@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org,
kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95
Date: Tue, 9 Jun 2026 21:17:33 +0530 [thread overview]
Message-ID: <xwupi3bxiihnmddqkdc6xsixkbirdpnips6qy5n4xchtcysnfq@f6pa5usw2a4f> (raw)
In-Reply-To: <20260518072715.3166514-2-hongxing.zhu@nxp.com>
On Mon, May 18, 2026 at 03:27:14PM +0800, Richard Zhu wrote:
> According to the i.MX95 PCIe PHY Databook, the ref_use_pad signal in the
> Common Block Signals section selects the reference clock source connected
> to the PHY pads. Per the specification, any change to this input must be
> followed by a PHY reset assertion to take effect.
>
> Move the REF_USE_PAD configuration before the PHY reset toggle to comply
> with the required initialization sequence.
>
> Fixes: 47f54a902dcd ("PCI: imx6: Toggle the core reset for i.MX95 PCIe")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 27 ++++++++++++++++++++++++---
> 1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 002e0a0d9382..66e760015c92 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
> const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
> const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
> const struct pci_epc_features *epc_features;
> + int (*init_pre_reset)(struct imx_pcie *pcie);
I renamed the callback and helper while applying:
s/init_pre_reset/select_ref_clk_src
- Mani
> int (*init_phy)(struct imx_pcie *pcie);
> int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
> int (*core_reset)(struct imx_pcie *pcie, bool assert);
> @@ -249,6 +250,24 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
> return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
> }
>
> +static int imx95_pcie_init_pre_reset(struct imx_pcie *imx_pcie)
> +{
> + bool ext = imx_pcie->enable_ext_refclk;
> +
> + /*
> + * Regarding the Signal Descriptions of i.MX95 PCIe PHY, ref_use_pad is
> + * used to select reference clock connected to a pair of pads.
> + *
> + * Any change in this input must be followed by phy_reset assertion.
> + */
> +
> + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
> + IMX95_PCIE_REF_USE_PAD,
> + ext ? IMX95_PCIE_REF_USE_PAD : 0);
> +
> + return 0;
> +}
> +
> static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> {
> bool ext = imx_pcie->enable_ext_refclk;
> @@ -271,9 +290,6 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
> IMX95_PCIE_PHY_CR_PARA_SEL,
> IMX95_PCIE_PHY_CR_PARA_SEL);
>
> - regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
> - IMX95_PCIE_REF_USE_PAD,
> - ext ? IMX95_PCIE_REF_USE_PAD : 0);
> regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
> IMX95_PCIE_REF_CLKEN,
> ext ? 0 : IMX95_PCIE_REF_CLKEN);
> @@ -1348,6 +1364,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
> pp->bridge->disable_device = imx_pcie_disable_device;
> }
>
> + if (imx_pcie->drvdata->init_pre_reset)
> + imx_pcie->drvdata->init_pre_reset(imx_pcie);
> +
> imx_pcie_assert_core_reset(imx_pcie);
>
> if (imx_pcie->drvdata->init_phy)
> @@ -2047,6 +2066,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> .core_reset = imx95_pcie_core_reset,
> .init_phy = imx95_pcie_init_phy,
> + .init_pre_reset = imx95_pcie_init_pre_reset,
> .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> .enable_ref_clk = imx95_pcie_enable_ref_clk,
> .clr_clkreq_override = imx95_pcie_clr_clkreq_override,
> @@ -2102,6 +2122,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> .ltssm_mask = IMX95_PCIE_LTSSM_EN,
> .mode_off[0] = IMX95_PE0_GEN_CTRL_1,
> .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
> + .init_pre_reset = imx95_pcie_init_pre_reset,
> .init_phy = imx95_pcie_init_phy,
> .core_reset = imx95_pcie_core_reset,
> .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
>
> base-commit: 40b7f61a1a4d7fd18188f3f87e15ff5a90ce1d31
> --
> 2.37.1
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2026-06-09 15:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-18 7:27 [PATCH v2 0/2] PCI: imx6: Fix i.MX95 PCIe PHY initialization sequence Richard Zhu
2026-05-18 7:27 ` [PATCH v2 1/2] PCI: imx6: Configure REF_USE_PAD before PHY reset for i.MX95 Richard Zhu
2026-06-09 15:47 ` Manivannan Sadhasivam [this message]
2026-06-11 2:51 ` Hongxing Zhu
2026-05-18 7:27 ` [PATCH v2 2/2] PCI: imx6: Assert ref_clk_en after reference clock stabilizes on i.MX95 Richard Zhu
2026-06-04 19:34 ` Frank Li
2026-06-09 15:46 ` [PATCH v2 0/2] PCI: imx6: Fix i.MX95 PCIe PHY initialization sequence Manivannan Sadhasivam
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