From: Trevor Gamblin <tgamblin@baylibre.com>
To: linux-pwm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de,
michael.hennerich@analog.com, nuno.sa@analog.com,
devicetree@vger.kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
tgamblin@baylibre.com, dlechner@baylibre.com
Subject: [PATCH 2/2] pwm: axi-pwmgen: support version 2.00.a
Date: Thu, 14 Mar 2024 16:47:22 -0400 [thread overview]
Message-ID: <20240314204722.1291993-3-tgamblin@baylibre.com> (raw)
In-Reply-To: <20240314204722.1291993-1-tgamblin@baylibre.com>
This adds support for the AXI PWMGEN v2 IP block. This version is
nearly identical to v1 other than it supports up to 16 channels instead
of 4 and a few of the memory mapped registers have moved.
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
---
drivers/pwm/pwm-axi-pwmgen.c | 62 ++++++++++++++++++++++++++++--------
1 file changed, 49 insertions(+), 13 deletions(-)
diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
index 0c8f7f893a21..539625c404ac 100644
--- a/drivers/pwm/pwm-axi-pwmgen.c
+++ b/drivers/pwm/pwm-axi-pwmgen.c
@@ -32,16 +32,25 @@
#define AXI_PWMGEN_REG_CORE_MAGIC 0x0C
#define AXI_PWMGEN_REG_CONFIG 0x10
#define AXI_PWMGEN_REG_NPWM 0x14
-#define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (12 * (ch)))
-#define AXI_PWMGEN_CHX_DUTY(ch) (0x44 + (12 * (ch)))
-#define AXI_PWMGEN_CHX_OFFSET(ch) (0x48 + (12 * (ch)))
+#define AXI_PWMGEN_CHX_PERIOD(v, ch) ((v)->period_base + (v)->ch_step * (ch))
+#define AXI_PWMGEN_CHX_DUTY(v, ch) ((v)->duty_base + (v)->ch_step * (ch))
+#define AXI_PWMGEN_CHX_OFFSET(v, ch) ((v)->offset_base + (v)->ch_step * (ch))
#define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */
#define AXI_PWMGEN_LOAD_CONFIG BIT(1)
#define AXI_PWMGEN_RESET BIT(0)
+struct axi_pwm_variant {
+ u8 period_base;
+ u8 duty_base;
+ u8 offset_base;
+ u8 major_version;
+ u8 ch_step;
+};
+
struct axi_pwmgen_ddata {
struct regmap *regmap;
unsigned long clk_rate_hz;
+ const struct axi_pwm_variant *variant;
};
static const struct regmap_config axi_pwmgen_regmap_config = {
@@ -50,12 +59,30 @@ static const struct regmap_config axi_pwmgen_regmap_config = {
.val_bits = 32,
};
+static const struct axi_pwm_variant pwmgen_1_00_variant = {
+ .period_base = 0x40,
+ .duty_base = 0x44,
+ .offset_base = 0x48,
+ .major_version = 1,
+ .ch_step = 12,
+};
+
+static const struct axi_pwm_variant pwmgen_2_00_variant = {
+ .period_base = 0x40,
+ .duty_base = 0x80,
+ .offset_base = 0xC0,
+ .major_version = 2,
+ .ch_step = 4,
+};
+
+
static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
unsigned int ch = pwm->hwpwm;
struct regmap *regmap = ddata->regmap;
+ const struct axi_pwm_variant *variant = ddata->variant;
u64 period_cnt, duty_cnt;
int ret;
@@ -70,7 +97,7 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (period_cnt == 0)
return -EINVAL;
- ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt);
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(variant, ch), period_cnt);
if (ret)
return ret;
@@ -78,15 +105,15 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (duty_cnt > UINT_MAX)
duty_cnt = UINT_MAX;
- ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt);
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), duty_cnt);
if (ret)
return ret;
} else {
- ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0);
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(variant, ch), 0);
if (ret)
return ret;
- ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0);
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), 0);
if (ret)
return ret;
}
@@ -99,11 +126,12 @@ static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip);
struct regmap *regmap = ddata->regmap;
+ const struct axi_pwm_variant *variant = ddata->variant;
unsigned int ch = pwm->hwpwm;
u32 cnt;
int ret;
- ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt);
+ ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(variant, ch), &cnt);
if (ret)
return ret;
@@ -111,7 +139,7 @@ static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
- ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt);
+ ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(variant, ch), &cnt);
if (ret)
return ret;
@@ -127,7 +155,8 @@ static const struct pwm_ops axi_pwmgen_pwm_ops = {
.get_state = axi_pwmgen_get_state,
};
-static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
+static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev,
+ const struct axi_pwm_variant *variant)
{
int ret;
u32 val;
@@ -146,7 +175,7 @@ static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
if (ret)
return ret;
- if (ADI_AXI_PCORE_VER_MAJOR(val) != 1) {
+ if (ADI_AXI_PCORE_VER_MAJOR(val) != variant->major_version) {
return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n",
ADI_AXI_PCORE_VER_MAJOR(val),
ADI_AXI_PCORE_VER_MINOR(val),
@@ -178,9 +207,14 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
struct pwm_chip *chip;
struct axi_pwmgen_ddata *ddata;
struct clk *clk;
+ const struct axi_pwm_variant *variant;
void __iomem *io_base;
int ret;
+ variant = device_get_match_data(dev);
+ if (!variant)
+ return -EINVAL;
+
io_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(io_base))
return PTR_ERR(io_base);
@@ -190,7 +224,7 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(regmap),
"failed to init register map\n");
- ret = axi_pwmgen_setup(regmap, dev);
+ ret = axi_pwmgen_setup(regmap, dev, variant);
if (ret < 0)
return ret;
@@ -199,6 +233,7 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
return PTR_ERR(chip);
ddata = pwmchip_get_drvdata(chip);
ddata->regmap = regmap;
+ ddata->variant = variant;
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
@@ -224,7 +259,8 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
}
static const struct of_device_id axi_pwmgen_ids[] = {
- { .compatible = "adi,axi-pwmgen-1.00.a" },
+ { .compatible = "adi,axi-pwmgen-1.00.a", .data = &pwmgen_1_00_variant },
+ { .compatible = "adi,axi-pwmgen-2.00.a", .data = &pwmgen_2_00_variant },
{ }
};
MODULE_DEVICE_TABLE(of, axi_pwmgen_ids);
--
2.44.0
next prev parent reply other threads:[~2024-03-14 20:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-14 20:47 [PATCH 0/2] pwm: axi-pwmgen: Add support for v2 IP Trevor Gamblin
2024-03-14 20:47 ` [PATCH 1/2] dt-bindings: pwm: adi,axi-pwmgen: Add compatible " Trevor Gamblin
2024-03-14 21:12 ` Krzysztof Kozlowski
2024-03-14 20:47 ` Trevor Gamblin [this message]
2024-03-15 11:54 ` [PATCH 2/2] pwm: axi-pwmgen: support version 2.00.a Nuno Sá
2024-04-14 9:05 ` Uwe Kleine-König
2024-04-15 13:58 ` Trevor Gamblin
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