From: Billy Tsai <billy_tsai@aspeedtech.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>,
"andrew@aj.id.au" <andrew@aj.id.au>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
"joel@jms.id.au" <joel@jms.id.au>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
BMC-SW <BMC-SW@aspeedtech.com>,
"lee.jones@linaro.org" <lee.jones@linaro.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [v5 2/2] pwm: Add Aspeed ast2600 PWM support
Date: Mon, 17 May 2021 06:23:06 +0000 [thread overview]
Message-ID: <C451B628-C0CC-47E9-84EF-42DB8518FE1E@aspeedtech.com> (raw)
In-Reply-To: <20210517060615.3hyifoebyrddsrta@pengutronix.de>
Hi,
On 2021/5/17, 2:06 PM,Uwe Kleine-Königwrote:
On Mon, May 17, 2021 at 02:53:44AM +0000, Billy Tsai wrote:
> > On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote:
> >
> > > > + div_h = DIV_ROUND_DOWN_ULL(div_h,
> > > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1));
> > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC);
> >
> > > As a division is an expensive operation you can better first multiply
> > > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by
> > > the result.
> >
> > When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow
> > for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue.
> > Can you give me some suggests?
> Hmm, you're right. There doesn't seem to be a div64_64, I thought there
> was one. Anyhow, while looking at the various divide functions I saw
> that dividing by a constant shouldn't be that expensive, so I think the
> sane way is to keep the two divisions and add a comment describing the
> problem.
According to our fixed value, I think that I can use bit shift to reduce one divide function:
rate = clk_get_rate(priv->clk);
/* Get the smallest value for div_h */
div_h = rate * state->period;
div_h >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) +
__fls(FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1));
div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC);
div_h = order_base_2(div_h);
if (div_h > 0xf)
div_h = 0xf;
div_l = rate * state->period;
div_l >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) + div_h);
div_l = DIV_ROUND_DOWN_ULL(div_l, NSEC_PER_SEC);
How about this change of the driver?
Thanks
next prev parent reply other threads:[~2021-05-17 6:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 2:48 [v5 0/2] Support pwm driver for aspeed ast26xx Billy Tsai
2021-05-14 2:48 ` [v5 1/2] dt-bindings: Add bindings for aspeed pwm-tach Billy Tsai
2021-05-14 2:48 ` [v5 2/2] pwm: Add Aspeed ast2600 PWM support Billy Tsai
2021-05-15 15:18 ` Uwe Kleine-König
2021-05-17 2:53 ` Billy Tsai
2021-05-17 6:06 ` Uwe Kleine-König
2021-05-17 6:23 ` Billy Tsai [this message]
2021-05-17 6:35 ` Uwe Kleine-König
2021-05-17 7:12 ` Billy Tsai
2021-05-17 17:10 ` Uwe Kleine-König
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