From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: MIME-Version: 1.0 References: <20210428001946.1059426-1-roman.beranek@prusa3d.com> <20210428061357.725m72aikc52n4gg@pengutronix.de> In-Reply-To: <20210428061357.725m72aikc52n4gg@pengutronix.de> From: =?UTF-8?Q?Roman_Ber=C3=A1nek?= Date: Wed, 28 Apr 2021 14:07:56 +0200 Message-ID: Content-Type: multipart/alternative; boundary="0000000000004cf6c005c1073b9b" Subject: Re: [PATCH] pwm: sun4i: Round delay time up to a nearest jiffy To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= Cc: Thierry Reding , Lee Jones , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com, Roman Beranek List-ID: --0000000000004cf6c005c1073b9b Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hello Uwe, Correct, the output may stay in an active state. I only discovered this bug as I investigated a report of unreliable screen timeout. The period we use the PWM with is 50 us. The PWMx_RDY bit stays 0 well after the last period ends, so if the bit has any function at all, this one is certainly not it. Cheers, Roman On Wed, Apr 28, 2021 at 8:14 AM Uwe Kleine-K=C3=B6nig < u.kleine-koenig@pengutronix.de> wrote: > Hello Roman, > > On Wed, Apr 28, 2021 at 02:19:46AM +0200, Roman Beranek wrote: > > More often than not, a PWM period may span nowhere near as far > > as 1 jiffy, yet it still must be waited upon before the channel > > is disabled. > > I wonder what happens if you don't wait long enough. Is this a > theoretical issue, or do you see an (occasional?) breakage that is fixed > by this patch? > > I guess the problem is that if you disable too early the output freezes > and that might be in a state where the output is still active? Would > polling the PWMx_RDY bit in the control register help here? > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-K=C3=B6nig = | > Industrial Linux Solutions | https://www.pengutronix.de/ = | > --0000000000004cf6c005c1073b9b Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello Uwe,

Cor= rect, the output may stay in an active state. I only discovered this
= bug as I investigated a report of unreliable screen timeout. The period
we use the PWM with is 50 us.

The PWMx_RDY bit stays 0 well after the last period ends, so if the bi= t
has any function at all, this on= e is certainly not it.

<= div style=3D"color:rgba(0,0,0,0.87);font-family:Roboto,RobotoDraft,Helvetic= a,Arial,sans-serif;font-size:14px">Cheers,
Roman

On Wed, Apr 28, 2021 at 8:14 AM Uwe Kleine-K=C3= =B6nig <u.kleine-koeni= g@pengutronix.de> wrote:
Hello Roman,

On Wed, Apr 28, 2021 at 02:19:46AM +0200, Roman Beranek wrote:
> More often than not, a PWM period may span nowhere near as far
> as 1 jiffy, yet it still must be waited upon before the channel
> is disabled.

I wonder what happens if you don't wait long enough. Is this a
theoretical issue, or do you see an (occasional?) breakage that is fixed by this patch?

I guess the problem is that if you disable too early the output freezes
and that might be in a state where the output is still active? Would
polling the PWMx_RDY bit in the control register help here?

Best regards
Uwe

--
Pengutronix e.K.=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| Uwe Kleine-K=C3=B6nig=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |
Industrial Linux Solutions=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0| https://www.pengutronix.de/ |
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