From: Claudiu <claudiu.beznea@tuxon.dev>
To: geert+renesas@glider.be, mturquette@baylibre.com,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
magnus.damm@gmail.com, ulf.hansson@linaro.org
Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: [PATCH v4 8/8] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
Date: Mon, 22 Apr 2024 13:53:55 +0300 [thread overview]
Message-ID: <20240422105355.1622177-9-claudiu.beznea.uj@bp.renesas.com> (raw)
In-Reply-To: <20240422105355.1622177-1-claudiu.beznea.uj@bp.renesas.com>
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
IP specific power domain as the driver has been modified to support
multiple power domains.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- used proper domain ID for IA55 interrupt controller
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index f5f3f4f4c8d6..bdd4f9376fc0 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -67,7 +67,7 @@ scif0: serial@1004b800 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
clock-names = "fck";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SCIF0>;
resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
@@ -79,7 +79,7 @@ cpg: clock-controller@11010000 {
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
- #power-domain-cells = <0>;
+ #power-domain-cells = <1>;
};
sysc: system-controller@11020000 {
@@ -104,7 +104,7 @@ pinctrl: pinctrl@11030000 {
interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
resets = <&cpg R9A08G045_GPIO_RSTN>,
<&cpg R9A08G045_GPIO_PORT_RESETN>,
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
@@ -177,7 +177,7 @@ irqc: interrupt-controller@11050000 {
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_IA55>;
resets = <&cpg R9A08G045_IA55_RESETN>;
};
@@ -192,7 +192,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI0_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI0>;
status = "disabled";
};
@@ -207,7 +207,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI1_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI1>;
status = "disabled";
};
@@ -222,7 +222,7 @@ sdhi2: mmc@11c20000 {
<&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI2_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI2>;
status = "disabled";
};
@@ -239,7 +239,7 @@ eth0: ethernet@11c30000 {
<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -258,7 +258,7 @@ eth1: ethernet@11c40000 {
<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -284,7 +284,7 @@ wdt0: watchdog@12800800 {
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G045_WDT0_PRESETN>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_WDT0>;
status = "disabled";
};
};
--
2.39.2
next prev parent reply other threads:[~2024-04-22 10:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-22 10:53 [PATCH v4 0/8] clk: renesas: rzg2l: Add support for power domains Claudiu
2024-04-22 10:53 ` [PATCH v4 1/8] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs Claudiu
2024-04-22 10:53 ` [PATCH v4 2/8] dt-bindings: clock: r9a07g044-cpg: " Claudiu
2024-04-22 10:53 ` [PATCH v4 3/8] dt-bindings: clock: r9a07g054-cpg: " Claudiu
2024-04-22 10:53 ` [PATCH v4 4/8] dt-bindings: clock: r9a08g045-cpg: " Claudiu
2024-04-22 10:53 ` [PATCH v4 5/8] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S Claudiu
2024-04-22 10:53 ` [PATCH v4 6/8] clk: renesas: rzg2l: Extend power domain support Claudiu
2024-04-24 14:09 ` Geert Uytterhoeven
2024-04-22 10:53 ` [PATCH v4 7/8] clk: renesas: r9a08g045: Add support for power domains Claudiu
2024-04-24 14:10 ` Geert Uytterhoeven
2024-04-22 10:53 ` Claudiu [this message]
2024-04-24 14:33 ` [PATCH v4 0/8] clk: renesas: rzg2l: " Geert Uytterhoeven
2024-04-25 16:44 ` Ulf Hansson
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