From: <conor.dooley@microchip.com>
To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>,
<robh+dt@kernel.org>, <jassisinghbrar@gmail.com>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <a.zummo@towertech.it>,
<alexandre.belloni@bootlin.com>, <broonie@kernel.org>,
<gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>,
<u.kleine-koenig@pengutronix.de>, <lee.jones@linaro.org>,
<linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>,
<linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org>
Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>,
<bin.meng@windriver.com>, <heiko@sntech.de>,
<lewis.hanly@microchip.com>, <conor.dooley@microchip.com>,
<daire.mcnamara@microchip.com>, <ivan.griffin@microchip.com>,
<atish.patra@wdc.com>
Subject: [PATCH v2 13/17] riscv: dts: microchip: use hart and clk defines for icicle kit
Date: Fri, 17 Dec 2021 09:33:21 +0000 [thread overview]
Message-ID: <20211217093325.30612-14-conor.dooley@microchip.com> (raw)
In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com>
From: Conor Dooley <conor.dooley@microchip.com>
Update the Microchip Icicle kit device tree by replacing interrupt and
clock related magic numbers with their defined counterparts.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 2 +-
.../boot/dts/microchip/microchip-mpfs.dtsi | 55 +++++++++++--------
2 files changed, 34 insertions(+), 23 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 0c748ae1b006..6d19ba196f12 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -31,7 +31,7 @@ cpus {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- clocks = <&clkcfg 26>;
+ clocks = <&clkcfg CLK_DDRC>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 869aaf0d5c06..ce9151edd1b6 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -2,6 +2,8 @@
/* Copyright (c) 2020 Microchip Technology Inc */
/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "dt-bindings/interrupt-controller/riscv-hart.h"
/ {
#address-cells = <2>;
@@ -14,7 +16,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -22,6 +23,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -32,7 +34,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -48,6 +49,7 @@ cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -59,7 +61,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -75,6 +76,7 @@ cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -86,7 +88,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -102,6 +103,7 @@ cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -113,7 +115,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -129,6 +130,7 @@ cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
cpu4_intc: interrupt-controller {
@@ -165,11 +167,16 @@ cache-controller@2010000 {
clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
- <&cpu1_intc 3>, <&cpu1_intc 7>,
- <&cpu2_intc 3>, <&cpu2_intc 7>,
- <&cpu3_intc 3>, <&cpu3_intc 7>,
- <&cpu4_intc 3>, <&cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc HART_INT_M_SOFT>,
+ <&cpu0_intc HART_INT_M_TIMER>,
+ <&cpu1_intc HART_INT_M_SOFT>,
+ <&cpu1_intc HART_INT_M_TIMER>,
+ <&cpu2_intc HART_INT_M_SOFT>,
+ <&cpu2_intc HART_INT_M_TIMER>,
+ <&cpu3_intc HART_INT_M_SOFT>,
+ <&cpu3_intc HART_INT_M_TIMER>,
+ <&cpu4_intc HART_INT_M_SOFT>,
+ <&cpu4_intc HART_INT_M_TIMER>;
};
plic: interrupt-controller@c000000 {
@@ -178,11 +185,15 @@ plic: interrupt-controller@c000000 {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupts-extended = <&cpu0_intc HART_INT_M_EXT>,
+ <&cpu1_intc HART_INT_M_EXT>,
+ <&cpu1_intc HART_INT_S_EXT>,
+ <&cpu2_intc HART_INT_M_EXT>,
+ <&cpu2_intc HART_INT_S_EXT>,
+ <&cpu3_intc HART_INT_M_EXT>,
+ <&cpu3_intc HART_INT_S_EXT>,
+ <&cpu4_intc HART_INT_M_EXT>,
+ <&cpu4_intc HART_INT_S_EXT>;
riscv,ndev = <186>;
};
@@ -210,7 +221,7 @@ serial0: serial@20000000 {
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
- clocks = <&clkcfg 8>;
+ clocks = <&clkcfg CLK_MMUART0>;
status = "disabled";
};
@@ -222,7 +233,7 @@ serial1: serial@20100000 {
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
- clocks = <&clkcfg 9>;
+ clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
@@ -234,7 +245,7 @@ serial2: serial@20102000 {
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
- clocks = <&clkcfg 10>;
+ clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
@@ -246,7 +257,7 @@ serial3: serial@20104000 {
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
- clocks = <&clkcfg 11>;
+ clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
@@ -256,7 +267,7 @@ mmc: mmc@20008000 {
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>, <89>;
- clocks = <&clkcfg 6>;
+ clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
@@ -267,7 +278,7 @@ emac0: ethernet@20110000 {
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 4>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
#address-cells = <1>;
@@ -280,7 +291,7 @@ emac1: ethernet@20112000 {
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 5>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
status = "disabled";
clock-names = "pclk", "hclk";
#address-cells = <1>;
--
2.33.1
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next prev parent reply other threads:[~2021-12-17 9:34 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-17 9:33 [PATCH v2 00/17] Update the Icicle Kit device tree conor.dooley
2021-12-17 9:33 ` [PATCH v2 01/17] dt-bindings: interrupt-controller: create a header for RISC-V interrupts conor.dooley
2021-12-21 17:47 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 02/17] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2021-12-17 13:24 ` Geert Uytterhoeven
2021-12-17 14:21 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 03/17] dt-bindings: soc/microchip: make systemcontroller a mfd conor.dooley
2021-12-21 17:55 ` Rob Herring
2021-12-21 23:50 ` conor dooley
2021-12-17 9:33 ` [PATCH v2 04/17] mailbox: change mailbox-mpfs compatible string conor.dooley
2021-12-17 13:25 ` Geert Uytterhoeven
2021-12-17 9:33 ` [PATCH v2 05/17] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
2021-12-17 14:21 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 06/17] dt-bindings: rng: add bindings for microchip mpfs rng conor.dooley
2021-12-17 14:53 ` Krzysztof Kozlowski
2021-12-17 15:07 ` Krzysztof Kozlowski
2021-12-17 15:22 ` Conor.Dooley
2021-12-17 15:47 ` Krzysztof Kozlowski
2021-12-17 16:26 ` conor dooley
2021-12-17 9:33 ` [PATCH v2 07/17] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2021-12-17 14:21 ` Rob Herring
2021-12-20 14:37 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 08/17] dt-bindings: soc/microchip: add bindings for mpfs system services conor.dooley
2021-12-17 9:33 ` [PATCH v2 09/17] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2021-12-17 14:21 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 10/17] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley
2021-12-17 11:17 ` Mark Brown
2021-12-17 11:40 ` Conor.Dooley
2021-12-17 11:43 ` Mark Brown
2021-12-20 8:05 ` Conor.Dooley
2021-12-17 14:21 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 11/17] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley
2021-12-17 14:21 ` Rob Herring
2021-12-21 13:32 ` Rob Herring
2021-12-17 9:33 ` [PATCH v2 12/17] dt-bindings: pwm: add microchip corePWM binding conor.dooley
2021-12-17 14:21 ` Rob Herring
2021-12-17 14:58 ` Krzysztof Kozlowski
2021-12-17 9:33 ` conor.dooley [this message]
2021-12-17 13:40 ` [PATCH v2 13/17] riscv: dts: microchip: use hart and clk defines for icicle kit Geert Uytterhoeven
2021-12-17 9:33 ` [PATCH v2 14/17] riscv: dts: microchip: add fpga fabric section to " conor.dooley
2021-12-17 13:43 ` Geert Uytterhoeven
2021-12-17 15:32 ` Conor.Dooley
2021-12-17 16:00 ` Geert Uytterhoeven
2022-01-12 9:38 ` Conor.Dooley
2022-01-14 13:35 ` Conor.Dooley
2021-12-17 14:59 ` Krzysztof Kozlowski
2021-12-17 9:33 ` [PATCH v2 15/17] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
2021-12-17 15:04 ` Krzysztof Kozlowski
2021-12-17 15:23 ` Conor.Dooley
2021-12-17 9:33 ` [PATCH v2 16/17] riscv: dts: microchip: update peripherals in " conor.dooley
2021-12-17 9:33 ` [PATCH v2 17/17] MAINTAINERS: update riscv/microchip entry conor.dooley
2021-12-17 15:09 ` Krzysztof Kozlowski
2021-12-23 14:56 ` Conor.Dooley
2021-12-23 17:36 ` Palmer Dabbelt
2022-01-12 13:32 ` Lewis.Hanly
2021-12-17 9:48 ` [PATCH v2 00/17] Update the Icicle Kit device tree Geert Uytterhoeven
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