From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/3] riscv: nommu: remove PAGE_OFFSET hardcoding
Date: Sat, 6 Apr 2024 19:21:57 +0800 [thread overview]
Message-ID: <20240406112159.1634-2-jszhang@kernel.org> (raw)
In-Reply-To: <20240406112159.1634-1-jszhang@kernel.org>
Currently, PAGE_OFFSET is hardcoded as 0x8000_0000, it works fine since
there's only one nommu platform in the mainline. However, there are
many cases where the (S)DRAM base address isn't 0x8000_0000, so remove
the hardcoding value, and introduce DRAM_BASE which will be set by
users during configuring. DRAM_BASE is 0x8000_0000 by default.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/Kconfig | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7895c77545f1..b4af1df86352 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -247,10 +247,16 @@ config MMU
Select if you want MMU-based virtualised addressing space
support by paged memory management. If unsure, say 'Y'.
+if !MMU
+config DRAM_BASE
+ hex '(S)DRAM Base Address'
+ default 0x80000000
+endif
+
config PAGE_OFFSET
hex
default 0xC0000000 if 32BIT && MMU
- default 0x80000000 if !MMU
+ default DRAM_BASE if !MMU
default 0xff60000000000000 if 64BIT
config KASAN_SHADOW_OFFSET
--
2.43.0
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next prev parent reply other threads:[~2024-04-06 11:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-06 11:21 [PATCH v2 0/3] riscv: improve nommu and timer-clint Jisheng Zhang
2024-04-06 11:21 ` Jisheng Zhang [this message]
2024-04-06 11:21 ` [PATCH v2 2/3] clocksource/drivers/timer-clint: Add option to use CSR instead of mtime Jisheng Zhang
2024-04-09 14:26 ` Conor Dooley
2024-04-09 14:48 ` Jisheng Zhang
2024-04-10 10:30 ` Jisheng Zhang
2024-04-24 11:01 ` Conor Dooley
2024-04-06 11:21 ` [PATCH v2 3/3] clocksource/drivers/timer-clint: Add T-Head C9xx clint Jisheng Zhang
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