[PATCH V2] riscv: set trap vector earlier

From: "yang.zhang" <gaoshanliukou@163.com>
To: alexghiti@rivosinc.com
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	"yang.zhang" <yang.zhang@hexintek.com>
Subject: [PATCH V2] riscv: set trap vector earlier
Date: Mon,  6 May 2024 10:22:39 +0800	[thread overview]
Message-ID: <20240506022239.6817-1-gaoshanliukou@163.com> (raw)

From: "yang.zhang" <yang.zhang@hexintek.com>

If trap earlier, trap vector doesn't yet set properly, current
value maybe set by previous firmwire, typically it's the _start of kernel,
it's confused and difficult to debuge, so set it earlier.
---
v1 -> v2:
As Alex commented, remove the patch for supporting hugesize kernek image
Add the omissive logic of set trap vector earlier

Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
---
 arch/riscv/kernel/head.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4236a69c35cb..03dc440e643e 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -300,6 +300,9 @@ SYM_CODE_START(_start_kernel)
 #else
 	mv a0, a1
 #endif /* CONFIG_BUILTIN_DTB */
+	/* Set trap vector to spin forever to help debug */
+	la a3, .Lsecondary_park
+	csrw CSR_TVEC, a3
 	call setup_vm
 #ifdef CONFIG_MMU
 	la a0, early_pg_dir
-- 
2.25.1


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