From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Rob Herring <robh+dt@kernel.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Geert Uytterhoeven <geert@linux-m68k.org>
Subject: [PATCH v3 09/11] riscv: dts: sifive: Group tuples in register properties
Date: Fri, 17 Dec 2021 13:49:30 +0100 [thread overview]
Message-ID: <333f37a8c2a6181d66172a06b3705a0551143c9c.1639744905.git.geert@linux-m68k.org> (raw)
In-Reply-To: <cover.1639744905.git.geert@linux-m68k.org>
To improve human readability and enable automatic validation, the tuples
in "reg" properties containing register blocks should be grouped using
angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
v3:
- No changes,
v2:
- Add Reviewed-by.
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 0caca0ccf6711ded..e2efcf08210926f8 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -196,8 +196,8 @@ i2c0: i2c@10030000 {
};
qspi0: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000
- 0x0 0x20000000 0x0 0x10000000>;
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <51>;
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -207,8 +207,8 @@ qspi0: spi@10040000 {
};
qspi1: spi@10041000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000
- 0x0 0x30000000 0x0 0x10000000>;
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -230,8 +230,8 @@ eth0: ethernet@10090000 {
compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>;
interrupts = <53>;
- reg = <0x0 0x10090000 0x0 0x2000
- 0x0 0x100a0000 0x0 0x1000>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
--
2.25.1
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next prev parent reply other threads:[~2021-12-17 12:49 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-17 12:49 [PATCH v3 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 01/11] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 02/11] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
2021-12-17 15:10 ` Krzysztof Kozlowski
2021-12-17 12:49 ` [PATCH v3 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 08/11] riscv: dts: sifive: " Geert Uytterhoeven
2021-12-17 12:49 ` Geert Uytterhoeven [this message]
2021-12-17 12:49 ` [PATCH v3 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
2021-12-17 12:49 ` [PATCH v3 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Geert Uytterhoeven
2022-01-09 18:21 ` [PATCH v3 00/11] riscv: dts: Miscellaneous fixes Palmer Dabbelt
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