From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@atishpatra.org>
Cc: "linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atishp@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Damien Le Moal <damien.lemoal@wdc.com>,
DTML <devicetree@vger.kernel.org>,
Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [v5 9/9] MAINTAINERS: Add entry for RISC-V PMU drivers
Date: Tue, 18 Jan 2022 11:01:03 +0530 [thread overview]
Message-ID: <CAAhSdy1cyGwwq6BDO5Xv_TfR6Pbk26hKDWQZSUWKTTX0A6iHxw@mail.gmail.com> (raw)
In-Reply-To: <20211225054647.1750577-10-atishp@rivosinc.com>
On Sat, Dec 25, 2021 at 11:17 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> From: Atish Patra <atish.patra@wdc.com>
>
> Add myself and Anup as maintainer for RISC-V PMU drivers.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9af529acb6a6..6232ae05e12c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16056,6 +16056,15 @@ S: Maintained
> F: drivers/mtd/nand/raw/r852.c
> F: drivers/mtd/nand/raw/r852.h
>
> +RISC-V PMU DRIVERS
> +M: Atish Patra <atishp@atishpatra.org>
> +M: Anup Patel <anup@brainfault.org>
Please use "R:" instead of "M:" for me.
> +L: linux-riscv@lists.infradead.org
> +S: Supported
> +F: drivers/perf/riscv_pmu.c
> +F: drivers/perf/riscv_pmu_legacy.c
> +F: drivers/perf/riscv_pmu_sbi.c
> +
> RISC-V ARCHITECTURE
> M: Paul Walmsley <paul.walmsley@sifive.com>
> M: Palmer Dabbelt <palmer@dabbelt.com>
> --
> 2.33.1
>
Regards,
Anup
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http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-01-18 5:31 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-25 5:46 [v5 0/9] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
2021-12-25 5:46 ` [v5 1/9] RISC-V: Remove the current perf implementation Atish Patra
2022-01-17 15:58 ` Anup Patel
2021-12-25 5:46 ` [v5 2/9] RISC-V: Add CSR encodings for all HPMCOUNTERS Atish Patra
2022-01-17 16:01 ` Anup Patel
2021-12-25 5:46 ` [v5 3/9] RISC-V: Add a perf core library for pmu drivers Atish Patra
2022-01-18 5:01 ` Anup Patel
2021-12-25 5:46 ` [v5 4/9] RISC-V: Add a simple platform driver for RISC-V legacy perf Atish Patra
2022-01-18 5:23 ` Anup Patel
2021-12-25 5:46 ` [v5 5/9] RISC-V: Add RISC-V SBI PMU extension definitions Atish Patra
2022-01-17 16:15 ` Anup Patel
2021-12-25 5:46 ` [v5 6/9] RISC-V: Add perf platform driver based on SBI PMU extension Atish Patra
2022-01-18 6:30 ` Anup Patel
2022-01-25 14:42 ` Eric Lin
2022-01-25 20:20 ` Atish Patra
2022-01-26 13:32 ` Eric Lin
2022-02-17 20:28 ` Atish Patra
2022-02-23 12:40 ` Eric Lin
2022-02-17 20:31 ` Atish Patra
2022-01-24 13:12 ` Heiko Stübner
2022-02-17 20:29 ` Atish Patra
2021-12-25 5:46 ` [v5 7/9] RISC-V: Add sscofpmf extension support Atish Patra
[not found] ` <CAKddAkCkbHLQS2XzH=+uz4gJG=ECMRZfd0P_5r48O0v0NT2yVQ@mail.gmail.com>
2022-01-05 7:43 ` Eric Lin
2022-01-05 21:34 ` Atish Patra
2021-12-25 5:46 ` [v5 8/9] Documentation: riscv: Remove the old documentation Atish Patra
2022-01-17 16:16 ` Anup Patel
2021-12-25 5:46 ` [v5 9/9] MAINTAINERS: Add entry for RISC-V PMU drivers Atish Patra
2022-01-18 5:31 ` Anup Patel [this message]
2021-12-25 6:12 ` [v5 0/9] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
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