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[209.85.216.47]) by smtp.gmail.com with ESMTPSA id e11sm8474746pjl.20.2021.12.17.05.51.13 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 05:51:13 -0800 (PST) Received: by mail-pj1-f47.google.com with SMTP id np6-20020a17090b4c4600b001a90b011e06so2821443pjb.5 for ; Fri, 17 Dec 2021 05:51:13 -0800 (PST) X-Received: by 2002:a1f:4641:: with SMTP id t62mr1041561vka.0.1639748601739; Fri, 17 Dec 2021 05:43:21 -0800 (PST) MIME-Version: 1.0 References: <20211217093325.30612-1-conor.dooley@microchip.com> <20211217093325.30612-15-conor.dooley@microchip.com> In-Reply-To: <20211217093325.30612-15-conor.dooley@microchip.com> From: Geert Uytterhoeven Date: Fri, 17 Dec 2021 14:43:10 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 14/17] riscv: dts: microchip: add fpga fabric section to icicle kit To: Conor Dooley Cc: Linus Walleij , Bartosz Golaszewski , Rob Herring , Jassi Brar , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alessandro Zummo , Alexandre Belloni , Mark Brown , Greg KH , Thierry Reding , =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Lee Jones , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Linux I2C , Linux PWM List , linux-riscv , Linux Crypto Mailing List , linux-rtc@vger.kernel.org, linux-spi , USB list , Krzysztof Kozlowski , Bin Meng , Heiko Stuebner , Lewis Hanly , daire.mcnamara@microchip.com, ivan.griffin@microchip.com, Atish Patra X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_055117_676237_FFE47704 X-CRM114-Status: GOOD ( 23.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Conor, On Fri, Dec 17, 2021 at 10:33 AM wrote: > From: Conor Dooley > > Split the device tree for the Microchip MPFS into two sections by adding > microchip-mpfs-fabric.dtsi, which contains peripherals contained in the > FPGA fabric. > > Signed-off-by: Conor Dooley Thanks for your patch! > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi > @@ -0,0 +1,13 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020-2021 Microchip Technology Inc */ > + > +/ { > + corePWM0: pwm@41000000 { > + compatible = "microchip,corepwm"; > + reg = <0x0 0x41000000 0x0 0xF0>; > + microchip,sync-update = /bits/ 8 <0>; > + #pwm-cells = <2>; > + clocks = <&clkcfg CLK_FIC3>; > + status = "disabled"; > + }; I'm wondering if these should be grouped under a "fabric" subnode, like we have an "soc" subnode for on-SoC devices? Rob? BTW, do you already have a naming plan for different revisions of FPGA fabric cores? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv