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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id b10sm1424506lfj.230.2021.12.17.06.58.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Dec 2021 06:58:36 -0800 (PST) Message-ID: Date: Fri, 17 Dec 2021 15:58:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.1 Subject: Re: [PATCH v2 12/17] dt-bindings: pwm: add microchip corePWM binding Content-Language: en-US To: conor.dooley@microchip.com, linus.walleij@linaro.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, jassisinghbrar@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, a.zummo@towertech.it, alexandre.belloni@bootlin.com, broonie@kernel.org, gregkh@linuxfoundation.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-crypto@vger.kernel.org, linux-rtc@vger.kernel.org, linux-spi@vger.kernel.org, linux-usb@vger.kernel.org Cc: geert@linux-m68k.org, bin.meng@windriver.com, heiko@sntech.de, lewis.hanly@microchip.com, daire.mcnamara@microchip.com, ivan.griffin@microchip.com, atish.patra@wdc.com References: <20211217093325.30612-1-conor.dooley@microchip.com> <20211217093325.30612-13-conor.dooley@microchip.com> From: Krzysztof Kozlowski In-Reply-To: <20211217093325.30612-13-conor.dooley@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211217_065839_973017_53133DCB X-CRM114-Status: GOOD ( 19.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 17/12/2021 10:33, conor.dooley@microchip.com wrote: > From: Conor Dooley > > Add device tree bindings for the Microchip fpga fabric based "core" PWM controller. > > Signed-off-by: Conor Dooley > --- > .../bindings/pwm/microchip,corepwm.yaml | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml > new file mode 100644 > index 000000000000..ed7d0351adc9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml > @@ -0,0 +1,61 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip ip core PWM controller bindings > + > +maintainers: > + - Conor Dooley > + > +description: | > + corePWM is an 16 channel pulse width modulator FPGA IP > + > + https://www.microsemi.com/existing-parts/parts/152118 > + > +properties: > + compatible: > + items: > + - const: microchip,corepwm > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + "#pwm-cells": > + const: 2 > + > + microchip,sync-update: > + description: | > + In synchronous mode, all channels are updated at the beginning of the PWM period. > + Asynchronous mode is relevant to applications such as LED control, where > + synchronous updates are not required. Asynchronous mode lowers the area size, > + reducing shadow register requirements. This can be set at run time, provided > + SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstream programmed > + to the device. Please also describe what is the meaning of the values used here. What does a value "2" mean? > + > + $ref: /schemas/types.yaml#/definitions/uint8 > + default: 0 > + > +required: > + - compatible > + - reg > + - clocks > + - "#pwm-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include "dt-bindings/clock/microchip,mpfs-clock.h" > + corePWN1: corePWM@41000000 { Here and in all patches, please skip the label. It's not helping. Node name: pwm > + compatible = "microchip,corepwm"; > + microchip,sync-update = /bits/ 8 <1>; > + clocks = <&clkcfg CLK_FIC3>; > + reg = <0x41000000 0xF0>; > + #pwm-cells = <2>; > + }; > Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv