From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Rob Herring <robh+dt@kernel.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Geert Uytterhoeven <geert@linux-m68k.org>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>
Subject: [PATCH v2 02/11] riscv: dts: canaan: Group tuples in interrupt properties
Date: Thu, 16 Dec 2021 14:37:26 +0100 [thread overview]
Message-ID: <d065b149b8c3e2af3de8953fdb15ef849ea4fce9.1639660956.git.geert@linux-m68k.org> (raw)
In-Reply-To: <cover.1639660956.git.geert@linux-m68k.org>
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
---
v2:
- Add Reviewed-by, Tested-by.
---
arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5e8ca8142482153b..56f57118c633b91a 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -103,8 +103,8 @@ rom0: nvmem@1000 {
clint0: timer@2000000 {
compatible = "canaan,k210-clint", "sifive,clint0";
reg = <0x2000000 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
plic0: interrupt-controller@c000000 {
@@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 {
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
riscv,ndev = <65>;
};
@@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 {
compatible = "canaan,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
- interrupts = <34 35 36 37 38 39 40 41
- 42 43 44 45 46 47 48 49
- 50 51 52 53 54 55 56 57
- 58 59 60 61 62 63 64 65>;
+ interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>, <45>, <46>, <47>,
+ <48>, <49>, <50>, <51>, <52>, <53>, <54>,
+ <55>, <56>, <57>, <58>, <59>, <60>, <61>,
+ <62>, <63>, <64>, <65>;
gpio-controller;
ngpios = <32>;
};
@@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 {
dmac0: dma-controller@50000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
- interrupts = <27 28 29 30 31 32>;
+ interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
clock-names = "core-clk", "cfgr-clk";
@@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 {
timer0: timer@502d0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
- interrupts = <14 15>;
+ interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
@@ -326,7 +327,7 @@ timer0: timer@502d0000 {
timer1: timer@502e0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
- interrupts = <16 17>;
+ interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
@@ -336,7 +337,7 @@ timer1: timer@502e0000 {
timer2: timer@502f0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
- interrupts = <18 19>;
+ interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
--
2.25.1
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next prev parent reply other threads:[~2021-12-16 13:45 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-16 13:37 [PATCH v2 00/11] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 01/11] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-12-16 13:37 ` Geert Uytterhoeven [this message]
2021-12-16 13:37 ` [PATCH v2 03/11] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 04/11] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
2021-12-16 14:39 ` Conor.Dooley
2021-12-16 13:37 ` [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node Geert Uytterhoeven
2021-12-16 14:47 ` Conor.Dooley
2021-12-16 13:37 ` [PATCH v2 07/11] riscv: dts: microchip: mpfs: Group tuples in interrupt properties Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 08/11] riscv: dts: sifive: " Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 09/11] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 10/11] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v2 11/11] riscv: dts: sifive: fu540-c000: Fix PLIC node Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
2021-12-16 13:43 ` Geert Uytterhoeven
2021-12-16 13:46 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:37 ` [PATCH v4 0/4] Renesas RZ/N1 NAND controller support Geert Uytterhoeven
2021-12-16 13:41 ` Geert Uytterhoeven
2021-12-16 13:43 ` Geert Uytterhoeven
2021-12-16 13:47 ` Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
2021-12-16 13:48 ` Geert Uytterhoeven
-- strict thread matches above, loose matches on Subject: below --
2021-12-16 13:41 [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive, plic: Miscellaneous improvements Geert Uytterhoeven
2021-12-16 13:41 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive, plic: Fix number of interrupts Geert Uytterhoeven
2021-12-16 21:29 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: " Rob Herring
2021-12-16 13:41 ` [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive, plic: Group interrupt tuples Geert Uytterhoeven
2021-12-16 21:29 ` [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive,plic: " Rob Herring
2021-12-16 21:28 ` [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements Rob Herring
2021-12-17 8:02 ` Geert Uytterhoeven
2021-12-16 13:43 [PATCH v2 0/2] dt-bindings: timer: sifive, clint: " Geert Uytterhoeven
2021-12-16 13:43 ` [PATCH v2 1/2] dt-bindings: timer: sifive, clint: Fix number of interrupts Geert Uytterhoeven
2021-12-16 21:30 ` [PATCH v2 1/2] dt-bindings: timer: sifive,clint: " Rob Herring
2021-12-16 13:43 ` [PATCH v2 2/2] dt-bindings: timer: sifive, clint: Group interrupt tuples Geert Uytterhoeven
2021-12-16 21:30 ` Rob Herring
2021-12-20 12:20 ` [PATCH v2 0/2] dt-bindings: timer: sifive,clint: Miscellaneous improvements Daniel Lezcano
2021-12-20 12:22 ` Daniel Lezcano
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